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參數(shù)資料
| 型號： | AD9228 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Quad, 12-bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| 中文描述： | 四，12位，六十五分之四十○MSPS的串行LVDS 1.8弗吉尼亞州/ D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 4/52頁 |
| 文件大?。?/td> | 1659K |
| 代理商： | AD9228 |
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AD9228
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = 0.5 dBFS, unless otherwise noted.
Table 2.
Parameter
1
SIGNAL-TO-NOISE RATIO (SNR)
f
IN
= 2.4 MHz
f
IN
= 19.7 MHz
f
IN
= 35 MHz
f
IN
= 70 MHz
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
f
IN
= 2.4 MHz
f
IN
= 19.7 MHz
f
IN
= 35 MHz
f
IN
= 70 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
f
IN
= 2.4 MHz
f
IN
= 19.7 MHz
f
IN
= 35 MHz
f
IN
= 70 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
IN
= 2.4 MHz
f
IN
= 19.7 MHz
f
IN
= 35 MHz
f
IN
= 70 MHz
WORST HARMONIC (Second or Third)
f
IN
= 2.4 MHz
f
IN
= 19.7 MHz
f
IN
= 35 MHz
f
IN
= 70 MHz
WORST OTHER (Excluding Second or Third)
f
IN
= 2.4 MHz
f
IN
= 19.7 MHz
f
IN
= 35 MHz
f
IN
= 70 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)—
AIN1 AND AIN2 = 7.0 dBFS
f
IN2
= 16 MHz
f
IN1
= 70 MHz,
f
IN2
= 71 MHz
1
See the
AN-835 Application Note
, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.
Rev. 0 | Page 4 of 52
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
AD9228-40
Min
Typ
70.5
68.5
70.2
70.2
70.0
70.3
68.0
69.8
69.7
69.5
11.4
11.1
11.37
11.37
11.33
85
72
82
80
80
85
82
80
80
90
90
90
90
80.8
AD9228-65
Min
Typ
70.2
70.0
68.5
70.0
69.5
70.0
70.0
68.0
69.8
69.0
11.37
11.33
11.1
11.33
11.25
85
85
73
84
74
85
85
84
74
90
90
90
88
77.8
Unit
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Max
72
80
Max
73
79
f
IN1
= 15 MHz,
25°C
75.0
77.0
dBc
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