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參數(shù)資料
| 型號： | AD9229BCP-50 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Quad 12-Bit, 50/65 MSPS Serial LVDS 3V A/D Converter |
| 中文描述： | 4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, QCC48 |
| 封裝： | MO-220-VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大小： | 471K |
| 代理商： | AD9229BCP-50 |
Quad 12-Bit, 50/65 MSPS
Serial LVDS 3V A/DConverter
Prelimnary Technical Data
AD9229
FEATURES
Four ADCs in one package
Serial LVDS digital output data rates (ANSI-644)
Data clock output provided
On Chip Reference and SHA
SNR = 70 dB at Fin up to Nyquist
Excellent Linearity:
DNL =
±
0.3 LSB (Typical)
INL =
±
0.6 LSB (Typical)
500 MHz full power analog bandwidth
Per Channel Core Power Dissipation = 270mW at 65MSPS /
200mW at 50MSPS
1 Vpp – 2 Vpp input voltage range
+3.0 V supply operation
Power down mode
APPLICATIONS
Digital beam forming systems in ultrasound
Wireless and wired broadband communications
Communications test equipment
Radar and satellite imaging sub-systems
FUNCTIONAL BLOCK DIAGRAM
Serial
LVDS
Pipeline
ADC
SHA
Data Rate
Multiplier
Ref
Select
+
-
0.5 V
Serial
LVDS
Pipeline
ADC
SHA
Serial
LVDS
Pipeline
ADC
SHA
Serial
LVDS
Pipeline
ADC
SHA
AD9229
D1+A
D1-A
LVDSBIAS
AGND
VREF
SENSE
VIN+A
VIN-A
VIN+B
VIN-B
VIN+C
VIN-C
VIN+D
VIN-D
AVDD
DRVDD
12
12
12
12
PDWN
DCO-
REFT
REFB
CLK
D1+B
D1-B
D1+C
D1-C
D1+D
D1-D
DRGND
DCO+
FCO-
Figure 1. Functional Block Diagram
PRODUCT DESCRIPTION
The AD9229 is a quad 12-bit monolithic sampling analog–to–
digital converter with an on–chip track–and–hold circuit and is
designed for low cost, low power, small size and ease of use. The
product operates up to a 65 MSPS conversion rate and is optimized
for outstanding dynamic performance where a small package size is
critical.
The ADC requires a single+3.0 V power supply and a TTL/CMOS
compatible sample rate clock for full performance operation. No
external reference or driver components are required for many
applications. A separate output power supply pin supports LVDS
compatible serial digital output levels.
The ADC automatically multiplies up the sample rate clock for the
appropriate LVDS serial data rate. An MSB trigger is provided to
signal a new output byte. Power down is supported and consumes
less than 3mW when enabled.
Fabricated on an advanced CMOS process, the AD9229 is available
in a 48-LFCSP package specified over the industrial temperature
range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1.
Four analog-to-digital converters are contained in one small,
space saving package.
2.
A Data Clock Output (DCO) is provided which operates up to
390 MHz.
3.
The outputs of each ADC are serialized with a maximum data
output rate of 780 Mbps (12-bits x 65 MSPS).
4.
The AD9229 operates from a single +3.0 V analog power
supply.
Rev. PrF 10/06/2003
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its
use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices. Trademarks and registered trademarks are the property
of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
2003 Analog Devices, Inc. All rights reserved.
www.analog.com
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