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參數(shù)資料
| 型號： | AD9224ARSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/15頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 40MSPS 28-SSOP |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 7 |
| 功率耗散（最大）： | 450mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
| 產(chǎn)品目錄頁面： | 780 (CN2011-ZH PDF) |
–3–
REV. A
AD9224
AC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D)
f
INPUT = 2.5 MHz
65
68.3
dB
f
INPUT = 10 MHz
63.5
68.0
dB
SIGNAL-TO-NOISE RATIO (SNR)
f
INPUT = 2.5 MHz
65.3
69.1
dB
f
INPUT = 10 MHz
64.6
68.4
dB
TOTAL HARMONIC DISTORTION (THD)
f
INPUT = 2.5 MHz
–80
–71
dB
f
INPUT = 10 MHz
–78
–67.4
dB
SPURIOUS FREE DYNAMIC RANGE
f
INPUT = 2.5 MHz
71.1
81
dB
f
INPUT = 10 MHz
67.9
79
dB
Full Power Bandwidth
120
MHz
Small Signal Bandwidth
120
MHz
Aperture Delay
1ns
Aperture Jitter
4
ps rms
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Parameters
Symbol
Min
Typ
Max
Units
LOGIC INPUTS
High Level Input Voltage
VIH
+3.5
V
Low Level Input Voltage
VIL
+1.0
V
High Level Input Current (VIN = DRVDD)
IIH
–10
+10
A
Low Level Input Current (VIN = 0 V)
IIL
–10
+10
A
Input Capacitance
CIN
5pF
LOGIC OUTPUTS (With DRVDD = 5 V)
High Level Output Voltage (IOH = 50
A)
VOH
+4.5
V
High Level Output Voltage (IOH = 0.5 mA)
VOH
+2.4
V
Low Level Output Voltage (IOL = 1.6 mA)
VOL
+0.4
V
Low Level Output Voltage (IOL = 50
A)
VOL
+0.1
V
Output Capacitance
COUT
5pF
LOGIC OUTPUTS (With DRVDD = 3 V)
High Level Output Voltage (IOH = 50
A)
VOH
+2.95
V
High Level Output Voltage (IOH = 0.5 mA)
VOH
+2.80
V
Low Level Output Voltage (IOL = 1.6 mA)
VOL
+0.4
V
Low Level Output Voltage (IOL = 50
A)
VOL
+0.05
V
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Parameters
Symbol
Min
Typ
Max
Units
Clock Period1
tC
25
ns
CLOCK Pulsewidth High
2
tCH
12.37
ns
CLOCK Pulsewidth Low
tCL
12.37
ns
Output Delay
tOD
13
ns
Pipeline Delay (Latency)
3
Clock Cycles
NOTES
1The clock period may be extended to 1 ms without degradation in specified performance @ +25
°C.
2
For operation at 40 MHz, the clock must be held to 50% duty cycle. See section on clock shaping in text.
Specifications subject to change without notice.
(AVDD = +5 V, DRVDD = +3 V, f
SAMPLE = 40 MSPS, VREF = 2.0 V, TMIN to TMAX, Differential Input unless otherwise noted)
(AVDD = +5 V, DRVDD = +5 V, unless otherwise noted)
(TMIN to TMAX with AVDD = + 5 V, DRVDD = +5 V, CL = 20 pF)
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