- 您現(xiàn)在的位置：買賣IC網 > PDF目錄10663 > AD9224ARSZ (Analog Devices Inc)IC ADC 12BIT 40MSPS 28-SSOP PDF資料下載
參數(shù)資料
| 型號： | AD9224ARSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 40MSPS 28-SSOP |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 7 |
| 功率耗散（最大）： | 450mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
| 產品目錄頁面： | 780 (CN2011-ZH PDF) |
AD9224
–9–
REV. A
Due to the high degree of symmetry within the SHA topology,
a significant improvement in distortion performance for differ-
ential input signals with frequencies up to and beyond Nyquist
can be realized. This inherent symmetry provides excellent
cancellation of both common-mode distortion and noise.
Also, the required input signal voltage span is reduced by a
half which further reduces the degree of RON modulation and
its effects on distortion.
The optimum noise and dc linearity performance for either
differential or single-ended inputs is achieved with the largest
input signal voltage span (i.e., 4 V input span) and matched
input impedance for VINA and VINB. Only a slight degrada-
tion in dc linearity performance exists between the 2 V and
4 V input spans.
Referring to Figure 14, the differential SHA is implemented
using a switched-capacitor topology. Its input impedance and
its switching effects on the input drive source should be consid-
ered in order to maximize the converter’s performance. The
combination of the pin capacitance, CPIN, parasitic capacitance
CPAR, and the sampling capacitance, CS, is typically less than
5 pF. When the SHA goes into track mode, the input source
must charge or discharge the voltage stored on CS to the new
input voltage. This action of charging and discharging CS,
averaged over a period of time and for a given sampling fre-
quency, FS, makes the input impedance appear to have a be-
nign resistive component. However, if this action is analyzed
within a sampling period (i.e., T = 1/FS), the input impedance
is dynamic and hence certain precautions on the input drive
source should be observed.
The resistive component to the input impedance can be com-
puted by calculating the average charge drawn by CH from the
input drive source. It can be shown that if CS is allowed to
fully charge up to the input voltage before switches QS1 are
opened, the average current into the input is the same as if
there were a resistor of 1/(CS FS) ohms connected between the
inputs. This means that the input impedance is inversely pro-
portional to the converter’s sample rate. Since CS is only 5 pF,
this resistive component is typically much larger than that of
the drive source (i.e., 5 k
at F
S = 40 MSPS).
The SHA’s input impedance over a sampling period appears as
a dynamic input impedance to the input drive source. When the
SHA goes into the track mode, the input source should ideally
provide the charging current through RON of switch QS1 in an
exponential manner. The requirement of exponential charging
means that the most common input source, an op amp, must
exhibit a source impedance that is both low and resistive up to
and beyond the sampling frequency.
The output impedance of an op amp can be modeled with a
series inductor and resistor. When a capacitive load is switched
onto the output of the op amp, the output will momentarily
drop due to its effective output impedance. As the output re-
covers, ringing may occur. To remedy the situation, a series
resistor can be inserted between the op amp and the SHA
input as shown in Figure 15. The series resistance helps isolate
the op amp from the switched-capacitor load.
10 F
VINA
VINB
SENSE
AD9224
0.1 F
RS
VCC
VEE
RS
VREF
REFCOM
Figure 15. Series Resistor Isolates Switched-Capacitor
SHA Input from Op Amp. Matching Resistors Improve
SNR Performance
The optimum size of this resistor is dependent on several fac-
tors, including the ADC sampling rate, the selected op amp,
and the particular application. In most applications, a 30
to
100
resistor is sufficient. However, some applications may
require a larger resistor value to reduce the noise bandwidth or
possibly limit the fault current in an overvoltage condition.
Other applications may require a larger resistor value as part of
an antialiasing filter. In any case, since the THD performance is
dependent on the series resistance and the above mentioned
factors, optimizing this resistor value for a given application is
encouraged.
The source impedance driving VINA and VINB should be
matched. Failure to provide that matching will result in the
degradation of the AD9224’s SNR, THD and SFDR.
For noise sensitive applications, the very high bandwidth of the
AD9224 may be detrimental and the addition of a series resistor
and/or shunt capacitor can help limit the wideband noise at the
A/D’s input by forming a low-pass filter. Note, however, that
the combination of this series resistance with the equivalent
input capacitance of the AD9224 should be evaluated for those
time domain applications that are sensitive to the input signal’s
absolute settling time. In applications where harmonic distor-
tion is not a primary concern, the series resistance may be
selected in combination with the nominal 10 pF of input
capacitance to set the filter’s 3 dB cutoff frequency.
A better method of reducing the noise bandwidth, while possi-
bly establishing a real pole for an antialiasing filter, is to add
some additional shunt capacitance between the input (i.e.,
VINA and/or VINB) and analog ground. Since this additional
shunt capacitance combines with the equivalent input capaci-
tance of the AD9224, a lower series resistance can be selected to
establish the filter’s cutoff frequency while not degrading the
distortion performance of the device. The shunt capacitance
also acts like a charge reservoir, sinking or sourcing the addi-
tional charge required by the hold capacitor, CH, further reduc-
ing current transients seen at the op amp’s output.
The effect of this increased capacitive load on the op amp driv-
ing the AD9224 should be evaluated. To optimize performance
when noise is the primary consideration, increase the shunt
capacitance as much as the transient response of the input signal
will allow. Increasing the capacitance too much may adversely
affect the op amp’s settling time, frequency response and distor-
tion performance.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9238BSTZ-40 | IC ADC 12BIT DUAL 40MSPS 64-LQFP |
| VI-J13-MW-F2 | CONVERTER MOD DC/DC 24V 100W |
| MAX9101ESA+T | IC COMPARATOR OD 8-SOIC |
| LTC1410CG#PBF | IC A/D CONV 12BIT SAMPLNG 28SSOP |
| VE-B1N-MX-F4 | CONVERTER MOD DC/DC 18.5V 75W |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9224ARSZRL | 功能描述:IC ADC 12BIT 40MSPS 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD9224-EB | 制造商:Analog Devices 功能描述:Evaluation Kit For Complete 12-Bit, 40 MSPS Monolithic A/D Converter 制造商:Analog Devices 功能描述:EVAL KIT FOR COMPLETE 12-BIT, 40 MSPS MONOLITHIC A/D CNVRTR - Bulk 制造商:Rochester Electronics LLC 功能描述:12-BIT 40 MSPS MONOLITHIC A/D CONVERTER - Bulk |
| AD9224JR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit |
| AD9224JRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit |
| AD9225 | 制造商:Analog Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。