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參數(shù)資料
| 型號： | AD9224ARSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 40MSPS 28-SSOP |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 40M |
| 數(shù)據接口： | 并聯(lián) |
| 轉換器數(shù)目： | 7 |
| 功率耗散（最大）： | 450mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
| 產品目錄頁面： | 780 (CN2011-ZH PDF) |
AD9224
–11–
REV. A
Table I. Analog Input Configuration Summary
Input
Input Range (V)
Figure
Connection
Coupling
Span (V)
VINA
1
VINB
1
#
Comments
Single-Ended
DC
2
0 to 2
1
19, 20
Best for stepped input response applications, requires
±5 V op amp.
2
× VREF
0 to
VREF
19, 20
Same as above but with improved noise performance due to
2
× VREF
increase in dynamic range. Headroom/settling time require-
ments of
±5 op amp should be evaluated.
4
0 to 4
2.0
19, 20
Optimum noise performance, excellent SNR performance, often
requires low distortion op amp with VCC > +5 V due to its head-
room issues.
2
× VREF
2.0 – VREF
2.0
30
Optimum THD performance with VREF = 1. Single supply
to
operation (i.e., +5 V) for many op amps.
2.0 + VREF
Single-Ended
AC
2 or
0 to 1 or
1 or VREF
21, 22
2
× VREF
0 to 2
× VREF
4
0.5 to 4.5
2.5
22
Optimum noise performance, excellent THD performance,
ability to use
±5 V op amp.
2
× VREF
2.0 – VREF
2.0
21
Flexible input range, Optimum THD performance with
to
VREF = 1. Ability to use either +5 V or
±5 V op amp.
2.0 + VREF
Differential
AC/DC
2
2 to 3
3 to 2
23, 24
Optimum full-scale THD and SFDR performance well beyond
(via Transformer)
the A/Ds Nyquist frequency. Preferred mode for undersampling
or Amplifier
applications.
2
× VREF
2.0 – VREF/2
2.0 + VREF/2
23, 24
Same as above with the exception that full-scale THD and SFDR
to
performance can be traded off for better noise performance.
2.0 + VREF/2
2.0 – VREF/2
4.0
1.5 to 3.5
3.5 to 1.5
23, 24
Optimum noise performance.
NOTE
1VINA and VINB can be interchanged if signal inversion is required.
Table II. Reference Configuration Summary
Reference
Input Span (VINA–VINB)
Operating Mode
(V p-p)
Required VREF (V)
Connect
To
INTERNAL
2
1
SENSE
VREF
INTERNAL
4
2
SENSE
REFCOM
INTERNAL
2
≤ SPAN ≤ 4 AND
1
≤ VREF ≤ 2.0 AND
R1
VREF AND SENSE
SPAN = 2
× VREF
VREF = (1 + R1/R2)
R2
SENSE AND REFCOM
EXTERNAL
2
≤ SPAN ≤ 41 ≤ VREF ≤ 2.0
SENSE
AVDD
(NONDYNAMIC)
VREF
EXT. REF.
EXTERNAL
2
≤ SPAN ≤ 4
CAPT and CAPB
SENSE
AVDD
(DYNAMIC)
Externally Driven
VREF
AVSS
EXT. REF.
CAPT
EXT. REF.
CAPB
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| AD9224ARSZRL | 功能描述:IC ADC 12BIT 40MSPS 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據采集 - 模數(shù)轉換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據接口:并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
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