參數(shù)資料
型號: AD9216BCPZRL7-65
廠商: Analog Devices Inc
文件頁數(shù): 8/40頁
文件大小: 0K
描述: IC ADC 10BIT DUAL 65MSPS 64LFCSP
標(biāo)準(zhǔn)包裝: 750
位數(shù): 10
采樣率(每秒): 65M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 240mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個單端,單極;2 個差分,單極
AD9216
Rev. A | Page 16 of 40
04775-027
–60
–50
–40
–30
–20
–10
0
TWO-TONE ANALOG INPUT LEVEL (dBFS)
dB
0
10
20
30
40
50
60
70
80
90
100
70dB REF LINE
TWO-TONE SFDR dBc
TWO-TONE SFDR dBFS
Figure 22. Two-Tone IMD Performance vs. Input Drive Level
(100.1 MHz and 101.1 MHz; fS = 105 MSPS (105 Grade); F1, F2 Levels Equal)
04775-
028
10
20
40
60
80
90
100
SAMPLE CLOCK RATE (MSPS)
CURRE
NT
(
m
A)
0
10
20
30
40
50
60
70
80
90
100
AVDD CURRENT (–105 GRADE)
AVDD CURRENT (–65/80 GRADE)
30
50
70
DRVDD CURRENT (ALL GRADES)
Figure 23. IAVDD, IDRVDD vs. Sample Clock Frequency,
CLOAD = 5 pF, AIN = 70 MHz @ 0.5 dBFS
04775-029
POSITIVE DUTY CYCLE (%)
dB
20
30
40
50
60
70
80
25
30
35
40
45
50
55
60
65
70
75
SFDR DCS ON
SFDR DCS
OFF
SNR DCS OFF
SNR DCS ON
Figure 24. SNR, SFDR vs. Positive Duty Cycle DCS Enabled, Disabled;
AIN = 70 MHz at 0.5 dBFS, 105 MSPS (105 Grade)
04775-030
VREF (V)
dB
0.25
0.35
0.45
0.55
0.65
0.75
0.85
0.95
1.05
1.15
1.25
40
45
50
55
60
65
70
75
80
SNR
SFDR
Figure 25. SNR, SFDR vs. External VREF (Full Scale = 2 × VREF)
AIN = 70.3 MHz at 0.5 dBFS, 105 MSPS (105 Grade)
04775-031
–40
–20
0
204060
80
TEMPERATURE (
°C)
GAIN
ERROR
(
%
Full
Scale)
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
INTERNAL REFERENCE MODE
EXTERNAL REFERENCE MODE
Figure 26. Typical Gain Error Variation vs. Temperature, (105 Grade)
AIN = 70 MHz at 0.5 dBFS, 105 MSPS (Normalized to 25°C)
04775-032
–40
–20
0
204060
80
TEMPERATURE (
°C)
dB
55
60
65
70
75
80
SFDR
SNR
SINAD
Figure 27. SNR, SINAD, SFDR vs. Temperature, (105 Grade)
AIN = 70 MHz at 0.5 dBFS, 105 MSPS, Internal Reference Mode
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