參數(shù)資料
型號(hào)： AD9216BCPZRL7-65
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/40頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT DUAL 65MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 10
采樣率（每秒）： 65M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 240mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)單端，單極；2 個(gè)差分，單極
AD9216
Rev. A | Page 26 of 40
DUAL ADC LFCSP PCB
The PCB requires a low jitter clock source, analog sources,
and power supplies. The PCB interfaces directly with ADI’s
standard dual-channel data capture board (HSC-ADC-EVAL-
DC), which together with ADI’s ADC Analyzer software
allows for quick ADC evaluation.
POWER CONNECTOR
Power is supplied to the board via three detachable
4-lead power strips.
Table 10. Power Connector
Terminal
Comments
VCC1 3.0 V
Analog supply for ADC
Output supply for ADC
Buffer supply
VCLK 3.0 V
Supply for XOR Gates
+5 V
Optional op amp supply
5 V
Optional op amp supply
1VCC, VDD, and VDL are the minimum required power connections.
ANALOG INPUTS
The evaluation board accepts a 2 V p-p analog input signal
centered at ground at two SMB connectors, Input A and
Input B. These signals are terminated at their respective
primary side transformer. T1 and T2 are wideband RF
transformers that provide the single-ended-to-differential
conversion, allowing the ADC to be driven differentially,
minimizing even-order harmonics. The analog signals can
be low-pass filtered at the secondary transformer to reduce
high frequency aliasing.
OPTIONAL OPERATIONAL AMPLIFIER
The PCB has been designed to accommodate an optional
AD8139 op amp that can serve as a convenient solution
for dc-coupled applications. To use the AD8139 op amp,
remove C14, R4, R5, C13, R37, and R36, and place R22, R23,
R30, and R24.
CLOCK
The single-clock input is at J5; the input clock is buffered and
drives both channel input clocks from Pin 3 at U8 through R79,
R40, and R85. Jumper E11 to E19 allows for inverting the input
clock. U8 also provides CLKA and CLKB outputs, which are
buffered by U6 and U5, which drive the DRA and DRB signals
(these are the data-ready clocks going off card). DRA and DRB
can also be inverted at their respective jumpers.
Table 11. Jumpers
Terminal
Comments
OEB A
Output Enable for A Side
PWDN A
Power-Down A
MUX
Mux Input
SHARED REF
Shared Reference Input
DRA
Invert DRA
LATA
Invert A Latch Clock
ENC A
Invert Encode A
OEB B
Output Enable for B Side
PWDN B
Power-Down B
DFS
Data Format Select
SHARED REF
Shared Reference Input
DRB
Invert DRB
LATB
Invert B Latch Clock
ENC B
Invert Encode B
VOLTAGE REFERENCE
The ADC SENSE pin is brought out to E41, and the internal
reference mode is selected by placing a jumper from E41 to
ground (E27). External reference mode is selected by placing a
jumper from E41 to E25 and E30 to E2. R56 and R45 allow for
programmable reference mode selection.
DATA OUTPUTS
The ADC outputs are buffered on the PCB at U2, U4. The ADC
outputs have the recommended series resistors in line to limit
switching transient effects on ADC performance.
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參數(shù)描述
AD9216BCPZRL7-80 功能描述:IC ADC 10BIT DUAL 80MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極
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