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| 型號： | AD9202 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 10-Bit, 32 MSPS, 90 mW CMOS A/D Converter(32MSPS,10位A/D轉(zhuǎn)換器) |
| 中文描述： | 完整的10位，32 MSPS的90毫瓦的CMOS A / D轉(zhuǎn)換（32MSPS，10位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 369K |
| 代理商： | AD9202 |
AD9202
–9–
REV. B
0
–9
1.0E+6
1.0E+9
10.0E+6
S
100.0E+6
–3
–6
FREQUENCY – Hz
–12
–15
–18
–21
–24
–27
Figure 13. Large Signal Frequency Response
25
20
–25
0
3.0
1.0
INPUT VOLTAGE – V
2.0
15
10
–5
–10
–15
5
0
–20
2.5
0.5
1.5
I
B
m
A
REFBS = 0.5V
REFTS = 2.5V
CLOCK = 32MHz
Figure 14. Input Bias Current vs. Input Voltage
APPLYING THE AD9202
THEORY OF OPERATION
The AD9202 implements a pipelined multistage architecture to
achieve high sample rate with low power. The AD9202 distrib-
utes the conversion over several smaller A/D subblocks, refining
the conversion with progressively higher accuracy as it passes
the results from stage to stage. As a consequence of the distrib-
uted conversion, the AD9202 requires a small fraction of the
1023 comparators used in a traditional flash type A/D. A
sample-and-hold function within each of the stages permits the
first stage to operate on a new input sample while the second,
third and fourth stages operate on the three preceding samples.
OPERATIONAL MODES
The AD9202 is designed to allow optimal performance in a
wide variety of imaging, communications and instrumentation
applications, including pin compatibility with the AD9200. To
realize this flexibility, internal switches on the AD9202 are used
to reconfigure the circuit into different modes. These modes are
selected by appropriate pin strapping. There are three parts of
the circuit affected by this modality: the voltage reference, the
reference buffer, and the analog input. The nature of the appli-
cation will determine which mode is appropriate: the descrip-
tions in the following sections, as well as in Table I, should
assist in choosing the desired mode.
Table I. Mode Selection
Input
Connect
Input
Span
MODE
Pin
REFSENSE
Pin
Modes
REF
REFTS
REFBS
Figure
TOP/BOTTOM
AIN
1 V
AVDD
Short REFSENSE, REFTS and VREF Together
AGND
18
AIN
2 V
AVDD
AGND
Short REFTS and VREF Together
AGND
19
CENTER SPAN
AIN
1 V
AVDD/2
Short VREF and REFSENSE Together
AVDD/2
AVDD/2
20
AIN
2 V
AVDD/2
AGND
No Connect
AVDD/2
AVDD/2
Differential
AIN Is Input 1
1 V
AVDD/2
Short VREF and REFSENSE Together
AVDD/2
AVDD/2
29
REFTS and
REFBS Are
Shorted Together
for Input 2
2 V
AVDD/2
AGND
No Connect
AVDD/2
AVDD/2
External Ref
AIN
2 V max
AVDD
AVDD
No Connect
Span = REFTS
– REFBS (2 V max)
Short to
VREFTF
21, 22
AGND
Short to
VREFBF
23
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