參數(shù)資料
型號(hào): AD9202
廠商: Analog Devices, Inc.
英文描述: Complete 10-Bit, 32 MSPS, 90 mW CMOS A/D Converter(32MSPS,10位A/D轉(zhuǎn)換器)
中文描述: 完整的10位,32 MSPS的90毫瓦的CMOS A / D轉(zhuǎn)換(32MSPS,10位的A / D轉(zhuǎn)換器)
文件頁數(shù): 5/24頁
文件大?。?/td> 369K
代理商: AD9202
AD9202
–5–
REV. B
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9202 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
With
Respect
to
Parameter
Min Max
Units
AVDD
DRVDD
AVSS
AVDD
MODE
CLK
Digital Outputs
AIN
VREF
REFSENSE
REFTF, REFTB
REFTS, REFBS
Junction Temperature
Storage Temperature
Lead Temperature
10 sec
AVSS
DRVSS
DRVSS
DRVDD
AVSS
AVSS
DRVSS
AVSS
AVSS
AVSS
AVSS
AVSS
–0.3 +6.5
–0.3 +6.5
–0.3 +0.3
–6.5 +6.5
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 DRVDD + 0.3 V
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
+150
–65 +150
V
V
V
V
V
V
V
V
V
V
V
°
C
°
C
+300
°
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Options*
Model
AD9202JRS
AD9202JRSRL
AD9202-EVAL
0
°
C to +70
°
C
0
°
C to +70
°
C
28-Lead SSOP
28-Lead SSOP (Reel) RS-28
Evaluation Board
RS-28
*RS = Shrink Small Outline.
DRVDD
AVSS
DRVSS
DRVSS
AVDD
AVDD
AVSS
AVSS
AVDD
REFTF
REFTS
AVDD
AVSS
AVDD
AVSS
REFBS
REFBF
AVSS
AVDD
AVSS
AVDD
AVSS
AVDD
AVSS
d. AIN
AVDD
AVSS
AVSS
AVDD
AVSS
AVDD
AVDD
AVSS
AVDD
AVSS
AVDD
AVSS
Figure 2. Equivalent Circuits
a. D0–D9, OTR
b. Three-State, Standby, Clamp
c. CLK
e. Reference
f. CLAMPIN
g. MODE
h. REFSENSE
i. VREF
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參數(shù)描述
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