參數(shù)資料
型號(hào)： AD9148-M5375-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 16/72頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9149, ADL5375
設(shè)計(jì)資源： AD9148-M5375-EBZ Schematic
AD9148-M5375-EBZ BOM
AD9148-M5375-EBZ Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： *
Data Sheet
AD9148
Rev. B | Page 23 of 72
SPI OPTIONS
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by the LSB first bit
(Register 0x00, Bit 6). The default is MSB first (LSB first = 0).
When LSB first = 0 (MSB first), the instruction and data bit must
be written from MSB to LSB. Multibyte data transfers in MSB-
first format start with an instruction byte that includes the register
address of the most significant data byte. Subsequent data bytes
should follow from the high address to the low address. In MSB-
first mode, the serial port internal byte address generator decrements
for each data byte of the multibyte communication cycle.
When LSB first = 1 (LSB first), the instruction and data bit must
be written from LSB to MSB. Multibyte data transfers in LSB-
first format start with an instruction byte that includes the register
address of the least significant data byte followed by multiple data
bytes. The serial port internal byte address generator increments
for each byte of the multibyte communication cycle.
The serial port controller data address decrements from the data
address written toward 0x00 for multibyte I/O operations if the
MSB-first mode is active. The serial port controller address
increments from the data address written toward 0x1F for
multibyte I/O operations if the LSB-first mode is active.
R/W A6
A5
A4 A3
A2
A1
A0
D7 D6N D5N
D00
D10
D20
D30
D7 D6N D5N
D00
D10
D20
D30
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
SDIO
SDO
08910-
041
CS
Figure 41. Serial Register Interface Timing MSB First
A0
A1
A2
A3 A4
A5
A6 R/W D00 D10 D20
D7N
D6N
D5N
D4N
D00 D10 D20
D7N
D6N
D5N
D4N
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
SDIO
SDO
08910-
042
CS
Figure 42. Serial Register Interface Timing LSB First
INSTRUCTION BIT 6
INSTRUCTION BIT 7
SCLK
SDIO
tDS
tDCSB
tDH
tPWH
tPWL
tSCLK
08910-
043
CS
Figure 43. Timing Diagram for SPI Register Write
DATA BIT n – 1
DATA BIT n
SCLK
SDIO
SDO
tDV
08910-
044
CS
Figure 44. Timing Diagram for SPI Register Read
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