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參數(shù)資料
| 型號： | AD9114-DPG2-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/52頁 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 8BIT LO PWR 40LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC® |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 串行 |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9114 |
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Data Sheet
AD9114/AD9115/AD9116/AD9117
Rev. C | Page 11 of 52
Pin No.
Mnemonic
Description
29
IOUTN
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
30
RLIN
Load Resistor (62.5 ) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
31
CMLI
I DAC Output Common-Mode Level. When the internal on-chip (IRCML) is enabled, this pin is connected to the
on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IRCML) is
disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor, see
the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 .
32
FSADJQ/AUXQ
Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full-scale
current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation
section. Nominal value for this external resistor is 4 k for 8 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QRSET) is enabled, this pin is the auxiliary Q DAC output.
33
FSADJI/AUXI
Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IRSET) is disabled, this pin is the full-scale
current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation
section. Nominal value for this external resistor is 4 k for 8 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on-chip (IRSET) is enabled, it is the auxiliary I DAC output.
34
REFIO
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
reference output when in internal reference mode (a 0.1 F capacitor to AVSS is required).
35
RESET/PINMD
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
36
SCLK/CLKMD
Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer, see
the Retimer section.
37
SDIO/FORMAT
Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down
to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement
input data format.
38
CS/PWRDN
Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for
the SPI port.
39
DB7 (MSB)
Digital Input (MSB).
40
DB6
Digital Input.
EP (EPAD)
The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.
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