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參數(shù)資料
| 型號： | AD9042CHIPS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 41 MSPS Monolithic A/D Converter |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, UUC31 |
| 封裝： | DIE-31 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大小： | 488K |
| 代理商： | AD9042CHIPS |
AD9042
REV. A
–13–
A dc-coupled input configuration (shown below) is limited by
the drive amplifier performance. T he AD9042’s on-chip refer-
ence is buffered using the OP279 dual, rail-to-rail operational
amplifier. T he resulting voltage is combined with the analog
source using an AD9631. Pending improvements in drive
amplifiers, this dc-coupled approach is limited to ~75 dB–80 dB
of dynamic performance depending on which drive amplifier is
used. T he AD9631 and OP279 run off
±
5 V.
21
SIGNAL
SOURCE
0–50pF
49.9
AD9631
50
200
0.1μF
OP279
(1/2)
OP279
(1/2)
571
1k
79
114
0.1μF
AD9042
AIN
V
OFFSET
V
REF
Figure 36. DC-Coupled Analog Input Circuit
Power Supplies
Care should be taken when selecting a power source. Linear
supplies are strongly recommended as switching supplies tend to
have radiated components that may be “received” by the
AD9042. Each of the power supply pins should be decoupled as
closely to the package as possible using 0.1
μ
F chip capacitors.
T he AD9042 has separate digital and analog +5 V pins. T he
analog supplies and the denoted AV
CC
digital supply pins are
denoted DV
CC
. Although analog and digital supplies may be
tied together, best performance is achieved when the supplies
are separate. T his is because the fast digital output swings can
couple switching noise back into the analog supplies. Note that
AV
CC
must be held within 5% of 5 volts, however the DV
CC
supply may be varied according to output digital logic family
(i.e., DV
CC
should be connected to the supply for the digital
circuitry).
Output Loading
Care must be taken when designing the data receivers for the
AD9042. It is recommended that the digital outputs drive a se-
ries resistor of 499 ohms followed by a CMOS gate like the
74AC574. T o minimize capacitive loading, there should only
be one gate on each output pin. An example of this is shown in
the evaluation board schematics shown in Figures 37 and 38.
T he digital outputs of the AD9042 have a unique constant slew
rate output stage. T he output slew rate is about 1 V/ns
independent of output loading. A typical CMOS gate combined
with PCB trace and through hole will have a load of approxi-
mately 10 pF. T herefore as each bit switches, 10 mA
the device. A full- scale transition can cause up to 120 mA (12
bits
×
10 mA/bit) of current to flow through the digital output
stage. T he series resistor will minimize the output currents that
can flow in the output stage. T hese switching currents are
confined between ground and the DV
CC
pin. Standard T T L
gates should be avoided since they can appreciably add to the
dynamic switching currents of the AD9042.
10
pF
×
1
V
1
ns
of dynamic current per bit will flow in or out of
Layout Information
T he schematic of the evaluation boards (Figures 37 and 38)
represents a typical implementation of the AD9042. T he pinout
of the AD9042 facilitates ease of use and the implementation of
high frequency/high resolution design practices. All of the
digital outputs are on one side of the packages while the other
sides contain all of the inputs. It is highly recommended that
high quality ceramic chip capacitors be used to decouple each
supply pin to ground directly at the device. Depending on
the configuration used for the encode and analog inputs, one or
more capacitors are required on those input pins. T he capacitors
used on the
ENCODE
and V
REF
pins must be a low inductance
chip capacitor as referenced previously in the data sheet.
Although a multilayer board is recommended, it is not required
to achieve good results. As shown in the DIP evaluation board
layout (Figures 39–42), the top layer forms a near solid ground
plane while the under side is used for routing signal. No vias
or jumpers are required to route signals in and out of the
AD9042AD. Each supply is decoupled to ground directly at the
device.
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate (broken only by the
insertion of the series resistor). Logic fanout for each bit should
be one CMOS gate.
E valuation Boards
T he evaluation board for the AD9042 is very straight forward
consisting of power, signal inputs and digital outputs. T he
evaluation board includes an onboard clock oscillator for the
encode; all the user must supply is power and an analog signal.
Power to the analog supply pins is connected via banana jacks.
T he analog supply powers the crystal oscillator and the AV
CC
pins of the AD9042. T he DV
CC
power is supplied via J3, the
digital interface. T his digital supply connection also powers the
digital gates on the PCB. By maintaining separate analog and
digital power supplies, degradation in SNR and SFDR is kept
to a minimum. T otal power requirement for either PCB is
approximately 140 mA. T his configuration allows for easy
evaluation of different logic families (i.e., connection to a 3.3
volt logic board).
T he analog input is connected via J2 and is capacitively coupled
to the AD9042 (see “Driving the Analog Input”). T he onboard
termination resistor is 60.4
. T his resistor in parallel with
AD9042’s input resistance (250
) provides a 50
load to the
analog source. If a different input impedance is required,
replace R1 by using the following equation
R
1
=
1
Z
250
T he analog input range of PCB is
±
0.5 volts (i.e., signal ac-
coupled to AD9042).
T he encode signal is generated using the onboard crystal
oscillator, U1. T he oscillator is socketed and may be replaced
by an external encode source via J1. If an external source is
used, it should be a high quality T T L source. A transformer
converts the single-ended T T L signal to a differential clock (see
“Encoding the AD9042”). Since the encode is coupled with a
1
1
where
Z
is desired input impedance.
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相關(guān)代理商/技術(shù)參數(shù) |
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