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參數(shù)資料
| 型號(hào)： | AD875 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit, 15 MHz, 185 mW CMOS A/D Converter(10位,15MHz,185mW A/D轉(zhuǎn)換器) |
| 中文描述： | 10位，15兆赫，185毫瓦的CMOS A / D轉(zhuǎn)換（10位，15MHz的，185mW的A / D轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 9/20頁(yè) |
| 文件大?。?/td> | 568K |
| 代理商： | AD875 |
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AD875
REV. 0
–9–
clock half cycle may necessitate the use of an external divide-by-
two circuit as shown in Figure 12.
R
Q
CLK
(TO AD875)
S
30MHz
+5V
+5V
D
Q
74XX74
Figure 12. Divide-By-Two Clock Input Circuit
The AD875 is designed to support a conversion rate of 15MHz;
running the part at slightly faster clock rates may be possible,
although at reduced performance levels. Conversely, some slight
performance improvements might be realized by clocking the
AD875 at slower clock rates.
The power dissipated by the correction logic and output buffers is
largely proportional to the clock frequency; running at reduced
clock rates provides a reduction in power consumption. Figure
13 illustrates this trade-off.
DIGITAL INPUTS AND OUTPUTS
Each of the AD875’s digital control inputs, MINV, LINV,
TEST MODE, THREE-STATE, and STBY is buffered with an
inverter powered from the DRV
DD
supply pins. With DRV
DD
set
20
140
10
160
5
200
15
180
P
CLOCK FREQUENCY – MHz
Figure 13. Typical Power Dissipation vs. Clock Frequency
to +5 V all digital inputs readily interface with 5 V CMOS logic.
For interfacing with lower voltage CMOS logic, DRV
DD
can be
set to 3.3 V effectively lowering the nominal input threshold of
all digital inputs to 3.3 V/2 = 1.65 V.
The AD875 provides several convenient digital input pins for
controlling the converter output format. By utilizing digital
input pins MINV and LINV, three digital output formats are
possible: binary, twos complement, and ones complement.
Another element of digital functionality is provided with the
TEST MODE pin. To facilitate in-circuit testing of the digital
portion of your application, a fixed digital pattern controlled by
a digital input is available. For TEST MODE = LOW, an
alternating 1010101010 pattern is established. This pattern is
further manipulated when used in conjunction with the LINV
and MINV pins (see Output Data Format, Table II below).
Table II. Output Data Format
Approx
AIN (V)
Test
Mode
Three
State
(MSB)
D9
(LSB)
D0
MINV
LINV
OVR
D8
D7
D6
D5
D4
D3
D2
D1
UNR
>4
4
3
2
<2
X
>4
4
3
2
<2
X
>4
4
3
2
<2
X
>4
4
3
2
<2
X
>4
2<AIN<4
<2
X
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
Z
1
1
1
0
0
1
0
0
0
1
1
0
1
1
1
0
0
1
0
0
0
1
1
0
Z
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
Z
1
1
0
0
0
1
1
1
0
0
0
1
0
0
1
1
1
0
0
0
1
1
1
0
Z
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
Z
1
1
0
0
0
1
1
1
0
0
0
1
0
0
1
1
1
0
0
0
1
1
1
0
Z
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
Z
1
1
0
0
0
1
1
1
0
0
0
1
0
0
1
1
1
0
0
0
1
1
1
0
Z
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
Z
1
1
0
0
0
1
1
1
0
0
0
1
0
0
1
1
1
0
0
0
1
1
1
0
Z
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
Z
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
Z
Z – High Impedance; X – Don’t Care; – Determined By AIN.
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