- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375247 > AD875 (Analog Devices, Inc.) 10-Bit, 15 MHz, 185 mW CMOS A/D Converter(10位,15MHz,185mW A/D轉(zhuǎn)換器) PDF資料下載
參數(shù)資料
| 型號(hào)： | AD875 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit, 15 MHz, 185 mW CMOS A/D Converter(10位,15MHz,185mW A/D轉(zhuǎn)換器) |
| 中文描述： | 10位，15兆赫，185毫瓦的CMOS A / D轉(zhuǎn)換（10位，15MHz的，185mW的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 568K |
| 代理商： | AD875 |
AD875
REV. 0
–8–
REFTF and REFBF is also recommended for optimum
performance. This reference configuration provides the lowest
cost solution but has several disadvantages including poor dc
power supply rejection and poor accuracy due to the variability
of the internal and external resistor values.
AD875
REFTS
REFTF
REFBF
REFBS
400
10μF
0.1μF
10μF
0.1μF
NC
NC
165 (±1%)
340 (±1%)
10μF
+5V
34
35
29
30
NC = NO CONNECT
2V
4V
Figure 8. Low Cost Reference Circuit
A higher performance solution employs a voltage regulator to
improve dc power supply rejection and absolute accuracy.
Figure 9 shows a LM317 adjustable regulator configured to
generate a 1.6 V output for REFBF. This output is also used to
generate the 3.6 V REFTF signal by multiplying the REFBF
signal by 2.25. Note that the AD817 op amp used to multiply
REFBF has been compensated to ensure stability while driving
the large capacitive load. The accuracy of this solution is limited
by the external resistors and the initial accuracy of the reference.
AD875
REFTS
REFTF
REFBF
REFBS
NC
NC
10
μ
F
0.1
μ
F
10
μ
F
0.1
μ
F
10
12.5k (
±
1%)
10k (
±
1%)
LM317L
V
OUT
ADJ
V
IN
0.1
μ
F
+5V
68
243
NC = NO CONNECT
AD817
34
35
29
30
22nF
3.6V
1.6V
Figure 9. Reference Circuit with Good PSRR
For optimal performance, a force sense or Kelvin configuration
can be used as shown in Figure 10. This circuit uses a high-
accuracy reference (AD589) and a dual op amp (OP295) to
maintain accuracy and minimize voltage drops which are
generated in the wire connections to the REFTF and REFBF
inputs. The output of the AD589 is increased to 1.6 V and
3.6 V at the outputs of the op amps as required. Both op amps
are compensated to maintain stability while driving the
decoupling capacitors required at the REFTF and REFBF pins.
These outputs, being connected in a feedback loop, tend to
cancel any errors caused by the voltage drops in the wires. Note
that if the REFTS and REFBS are not used in a force sense
configuration, they should be left unconnected and should not
be connected to REFTF and REFBF.
10
μ
F
0.1
μ
F
10
AD875
REFTS
REFTF
REFBS
REFBF
20k (
±
1%)
10k (
±
1%)
47nF
10
μ
F
0.1
μ
F
10
10k (
±
1%)
30k (
±
1%)
47nF
3.6V
1/2 OP295
1/2 OP295
1.6V
+5V
7.5k
AD589
0.1
μ
F
35
34
29
30
Figure 10. High Performance Reference Circuit Using
Kelvin Connections
Like any high resolution converter, the layout and decoupling of
the reference is critical. The actual voltage digitized by the AD875
is relative to the reference voltages. In Figure 11, for example,
the reference returns and the bypass capacitors are connected to
the shield of the incoming analog signal. Disturbances in the
ground of the analog input, which will be common-mode to the
REFTF, REFBF, and AIN pins because of the common ground,
are effectively removed by the AD875’s high common-mode
rejection.
High frequency noise sources, V
N1
and V
N2,
are shunted to
ground by decoupling capacitors. Any voltage drops between
the analog input ground and the reference bypassing points will
be treated as input signals by the converter via the reference
inputs. Consequently, the reference decoupling capacitors
should be connected to the same analog ground point used to
define the analog input voltage. (For further suggestions, see the
“Grounding and Layout Rules” section of the data sheet.)
AD875
REFTF
REFBF
30
34
39
40
4V
2V
V
N1
V
N2
VINA
VINB
Figure 11. Recommended Bypassing for the Reference
Inputs
CLOCK INPUT
The AD875 clock input is buffered internally with an inverter
powered from the DRV
DD
pin. This feature allows the AD875
to accommodate either +5 V or +3.3 V CMOS logic input
signal swings with the input threshold for the CLK pin
nominally at DRV
DD
/2.
The AD875’s pipelined architecture operates on both rising and
falling edges of the input clock. To minimize duty cycle variations
the recommended logic family to drive the clock input is high
speed CMOS (HC/HCT) logic. HCMOS logic provides both
symmetrical voltage threshold levels and sufficient rise and fall
times to support 15 MHz operation. The AD875’s minimum
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9000 | High Speed 6-Bit A/D Converter |
| AD9003A | 12Bit,1MSPS,A/D Converter(12位,1MSPS A/D轉(zhuǎn)換器) |
| AD9005B | 12-Bit, 10 MSPS A/D Converter(12位,10MSPS A/D轉(zhuǎn)換器) |
| AD9007 | 12-Bit, 10 MSPS A/D Converter(12位,10MSPS A/D轉(zhuǎn)換器) |
| AD9014 | 14-Bit,10MSPS A/D Converter(14位,10MSPS A/D轉(zhuǎn)換器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD875-EB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD875JST | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 10-Bit |
| ad875jst-reel | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel 制造商:Analog Devices 功能描述: |
| AD876 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit 20 MSPS 160 mW CMOS A/D Converter |
| AD876AR | 制造商:Analog Devices 功能描述:ADC Single Pipelined 20Msps 10-bit Parallel 28-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:IC, MONO 10-BIT ADC - Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。