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參數(shù)資料
| 型號(hào)： | AD875 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit, 15 MHz, 185 mW CMOS A/D Converter(10位,15MHz,185mW A/D轉(zhuǎn)換器) |
| 中文描述： | 10位，15兆赫，185毫瓦的CMOS A / D轉(zhuǎn)換（10位，15MHz的，185mW的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 568K |
| 代理商： | AD875 |
AD875
REV. 0
–6–
DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity (INL)
Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale.” The
point used as “zero” occurs 1/2 LSB before the first code
transition. “Full scale” is defined as a level 1 1/2 LSB beyond
the last code transition. The deviation is measured from the
center of each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) are guaranteed.
Offset Error
The first transition should occur at a level 1/2 LSB above
“zero.” Offset is defined as the deviation of the actual first code
transition from that point.
Gain Error
The first code transition should occur for an analog value 1/2
LSB above nominal negative full scale. The last transition
should occur for an analog value 1 1/2 LSB below the nominal
positive full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal
difference between the first and last code transitions.
Pipeline Delay (Latency)
The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every clock cycle.
Reference Force/Sense Offset
Resistance between the reference input and comparator input
tap points causes offset errors. These errors can be nulled out by
using the force-sense connection as shown in the Reference
Input section.
THEORY OF OPERATION
The AD875 uses a pipelined multistage architecture to achieve
high sample rate with low power. The multistage approach
distributes the conversion over several smaller A/D sub-blocks,
refining the conversion with progressively higher accuracy as it
passes the results from stage to stage. As a consequence of the
distributed conversion, the AD875 requires only a small fraction
of the 1023 comparators that would be required in a more
traditional 10-bit flash type A/D. A sample-and-hold (SHA)
function within each of the stages permits the first stage to
operate on a new sample of the input while the second and third
stages operate on the two preceding samples. This “assembly
line” operation on multiple samples, known as pipelining, allows
higher throughput at the cost of some delay, referred to as
latency. (See the output timing diagram.)
The detailed operation is as follows: the first stage makes a 4-bit
estimate of the analog input voltage by means of the first stage
A/D sub-block. The first stage estimate is converted to analog
form by the first stage D/A and subtracted from the original
input signal. The remainder, or residue, is the difference
between the first stage estimate and the actual analog input.
Next, the residue is amplified and passed to the second stage
where another A/D sub-block makes a 4-bit estimate of its
value. Again the analog version of the estimate is subtracted
from the signal and an even finer residue is generated. Finally,
the A/D sub-block in the last stage measures the value of this
second stage residue.
The A/D sub-blocks within each stage are actually 4-bit flash
converters. Ideally 3 bits in the second and third stages would
be sufficient for a 10-bit A/D. The additional bits allow for
digital correction of errors in preceding stages, reducing the
tolerances on the sub-block components and making a more
robust A/D. The reference ladders for all three of these flash
sub-blocks are wired in parallel and connected to the reference
pins of the AD875.
Inside the AD875 all signals are processed differentially. This
not only enhances the internal dynamic range of the
components but provides a high level of noise immunity in a
digital environment.
APPLYING THE AD875
DRIVING THE ANALOG INPUT
The high input resistance and low input capacitance features of
the AD875 simplify the current and settling time demands
placed on input drive circuitry. Figure 4 shows the equivalent
input circuit of the AD875.
+5V
≈
3-4pF
1.6pF
1
+V
2
1
AD875
1 = CLK
2 = CLK
AIN
AIN
39
40
Figure 4. AD875 Equivalent Input Structure
The full-scale input range is set by the voltage span, REFTF-
REFBF (see “Driving the Reference” section). The recommended
span should nominally be 2 V peak-to-peak. This span must
remain bounded by the minimum and maximum input range
(specified in the Analog Input section under DC Specifications).
Some example input ranges are given in Table I.
Table I. Input Range Examples
–Full Scale
= REFBF
(V)
+Full Scale
= REFTF
(V)
Input
Span
(V)
+1.6
+2.0
+2.1
+3.6
+4.0
+4.1
+2.0
+2.0
+2.0
While the input impedance of the AD875 is quite high, the
switched capacitor input structure results in a small dynamic
input current. In order to prevent gain variations as a result of
the input current, maintaining a source impedance of less than
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD875-EB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD875JST | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 10-Bit |
| ad875jst-reel | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel 制造商:Analog Devices 功能描述: |
| AD876 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit 20 MSPS 160 mW CMOS A/D Converter |
| AD876AR | 制造商:Analog Devices 功能描述:ADC Single Pipelined 20Msps 10-bit Parallel 28-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:IC, MONO 10-BIT ADC - Bulk |
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