VDD
參數(shù)資料
型號： AD8402ARZ50-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 2/32頁
文件大?。?/td> 0K
描述： IC POT DIG DUAL 50K 8BIT 14SOIC
標(biāo)準(zhǔn)包裝： 2,500
接片： 256
電阻（歐姆）： 50k
電路數(shù)： 2
溫度系數(shù)： 標(biāo)準(zhǔn)值 500 ppm/°C
存儲器類型： 易失
接口： 3 線 SPI（芯片選擇）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 14-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 14-SOICN
包裝： 帶卷 (TR)
AD8400/AD8402/AD8403
Rev. E | Page 10 of 32
ELECTRICAL CHARACTERISTICS—ALL VERSIONS
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, 40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 4.
Parameter
Symbol
Conditions
Min
Max
Unit
SWITCHING CHARACTERISTICS2, 3
Input Clock Pulse Width
tCH, tCL
Clock level high or low
10
ns
Data Setup Time
tDS
5
ns
Data Hold Time
tDH
5
ns
CLK to SDO Propagation Delay4
tPD
RL = 1 kΩ to 5 V, CL ≤ 20 pF
1
25
ns
CS Setup Time
tCSS
10
ns
CS High Pulse Width
tCSW
10
ns
Reset Pulse Width
tRS
50
ns
CLK Fall to CS Rise Hold Time
tCSH
0
ns
CS Rise to Clock Rise Setup
tCS1
10
ns
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.
The remaining resistor terminals are left open circuit.
3 See the timing diagram in Figure 3 for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and
timed from a voltage level of 1.6 V. Switching characteristics are measured using VDD = 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate
of 1 V/μs should be maintained.
4 Propagation delay depends on the value of VDD, RL, and CL (see the Applications section).
TIMING DIAGRAMS
DAC REGISTER LOAD
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
0
VDD
0V
SDI
CLK
VOUT
CS
0
109
2-
0
03
Figure 3. Timing Diagram
±1% ERROR BAND
±1%
tCSH
tCSS
tDH
Ax OR Dx
tPD_MIN
tPD_MAX
A'x OR D'x
1
0
1
0
1
0
VDD
0V
SDI
(DATA IN)
CLK
CS
VOUT
1
0
SDO
(DATA OUT)
tDS
tCH
tCS1
tCL
tS
tCSW
0
109
2-
0
04
Figure 4. Detailed Timing Diagram
±1%
±1% ERROR BAND
1
0
VDD
VDD/2
VOUT
tRS
tS
RS
01
09
2-
0
05
Figure 5. Reset Timing Diagram
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