參數(shù)資料
型號(hào)： AD8402ARZ50-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/32頁(yè)
文件大小： 0K
描述： IC POT DIG DUAL 50K 8BIT 14SOIC
標(biāo)準(zhǔn)包裝： 2,500
接片： 256
電阻（歐姆）： 50k
電路數(shù)： 2
溫度系數(shù)： 標(biāo)準(zhǔn)值 500 ppm/°C
存儲(chǔ)器類型： 易失
接口： 3 線 SPI（芯片選擇）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 14-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 14-SOICN
包裝： 帶卷 (TR)
AD8400/AD8402/AD8403
Rev. E | Page 24 of 32
APPLICATIONS
INVERTING GAIN (V/V)
256
128
0
0.1
1
10
96
64
32
160
192
224
DI
G
IT
A
L
CO
DE
(D
eci
mal
)
01
09
2-
05
3
The digital potentiometer (RDAC) allows many of the applica-
tions of a mechanical potentiometer to be replaced by a solid-
state solution offering compact size and freedom from vibration,
shock, and open contact problems encountered in hostile
environments. A major advantage of the digital potentiometer
is its programmability. Any settings can be saved for later recall
in system memory.
The two major configurations of the RDAC include the
potentiometer divider (basic 3-terminal application) and
the rheostat (2-terminal configuration) connections shown
Certain boundary conditions must be satisfied for proper
AD8400/AD8402/AD8403 operation. First, all analog signals
must remain within the GND to VDD range used to operate the
single-supply AD8400/AD8402/AD8403. For standard
potentiometer divider applications, the wiper output can be
used directly. For low resistance loads, buffer the wiper with
a suitable rail-to-rail op amp such as the OP291 or the OP279.
Second, for ac signals and bipolar dc adjustment applications,
a virtual ground is generally needed. Whichever method is used
to create the virtual ground, the result must provide the necessary
sink and source current for all connected loads, including
adequate bypass capacitance. Figure 41 shows one channel of
the AD8402 connected in an inverting programmable gain
amplifier circuit. The virtual ground is set at 2.5 V, which allows
the circuit output to span a ±2.5 V range with respect to virtual
ground. The rail-to-rail amplifier capability is necessary for the
widest output swing. As the wiper is adjusted from its midscale
reset position (80H) toward the A terminal (code FFH), the
voltage gain of the circuit is increased in successively larger
increments. Alternatively, as the wiper is adjusted toward the B
terminal (code 00H), the signal becomes attenuated. The plot in
Figure 54 shows the wiper settings for a 100:1 range of voltage
gain (V/V). Note the ±10 dB of pseudologarithmic gain around
0 dB (1 V/V). This circuit is mainly useful for gain adjustments
in the range of 0.14 V/V to 4 V/V; beyond this range the step
sizes become very large, and the resistance of the driving circuit
can become a significant term in the gain equation.
Figure 54. Inverting Programmable Gain Plot
ACTIVE FILTER
The state variable active filter is one of the standard circuits
used to generate a low-pass, high-pass, or band-pass filter.
The digital potentiometer allows full programmability of the
frequency, gain, and Q of the filter outputs. Figure 55 shows
the filter circuit using a 2.5 V virtual ground, which allows a
±2.5 VP input and output swing. RDAC2 and RDAC3 set the
LP, HP, and BP cutoff and center frequencies, respectively.
These variable resistors should be programmed with the same
data (as with ganged potentiometers) to maintain the best
Circuit Q. Figure 56 shows the measured filter response at the
band-pass output as a function of the RDAC2 and RDAC3
settings that produce a range of center frequencies from 2 kHz
to 20 kHz. The filter gain response at the band-pass output is
shown in Figure 57. At a center frequency of 2 kHz, the gain is
adjusted over a 20 dB to +20 dB range determined by RDAC1.
Circuit Q is adjusted by RDAC4. For more detailed reading on
the state variable active filter, see Analog Devices’ application
note AN-318.
A1
RDAC1
VIN
B
A2
A3
A4
RDAC4
B
10k
Ω
10k
Ω
OP279 × 2
RDAC2
RDAC3
B
0.01
μF
0.01
μF
BAND-
PASS
HIGH-
PASS
LOW-
PASS
0
1
092-
054
Figure 55. Programmable State Variable Active Filter
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