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參數(shù)資料
| 型號： | AD8380JS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | Fast, High-Voltage Drive, 6-Channel Output DecDriver Decimating LCD Panel Driver |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, PQFP44 |
| 封裝： | 10 X 10 MM, 2 MM HEIGHT, MQFP-44 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 219K |
| 代理商： | AD8380JS |
REV. B
–3–
AD8380
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
2–11
12
NC
DB[0:9]
E/
O
No Connect.
Video Data Inputs. DB9 is the MSB.
Even/Odd data select, input latches are loaded at the falling edge of CLK if E/
O
is low or
rising edge if E/
O
is high.
Determines starting point of internally generated channel-loading sequence.
R/
L
Low (when address = 111) loads from Channel 0 up to Channel 5.
When high, analog video outputs are above the VMID setpoint. See Figure 3.
Digital Supplies. Nominally 3.3 V and 0 V, respectively.
13
R/
L
14
15, 16
17, 20, 22, 24,
26, 28, 30, 32,
34, 37, 38
18
INV
DVEE, DVCC
AVCCxxx, AVEExxx Analog Supplies. Nominally 15 V and 0 V, respectively.
STBY
Stand By. When high, all digital and analog circuits are “debiased” and the power dissipation
drops to a minimum.
BYP
An external capacitor connected from here to V
EE
will help to ensure rapid DAC settling time.
VMID
Externally supplied voltage applied here sets the midpoint reference for the video output.
19
21
23, 25, 27, 29,
31, 33
36, 35
VID5–VID0
VREFHI, VREFLO Voltage between these pins sets DAC full-scale range. An external reference must be applied
and should be common to all devices to ensure best tracking.
A[0:2]
3-bit channel address for addressable loading of the digital input latches.
STSQ/CS
STSQ to start internal sequencing or Chip Select to enable addressable channel addressing.
See functional description. Used in conjunction with A[0:2].
XFR
If XFR = HIGH at the rising edge of CLK, data is transferred to the DACs on the next falling
edge of CLK. See Figures 4, 6, 7, and 8.
CLK
Master Clock Input.
Analog Video Outputs.
39–41
42
43
44
CHANNEL SELECTION FUNCTIONALITY
There are two channel selection modes, addressed channel
loading, (in which the user directly controls which DAC is
loaded), and internally sequenced loading (in which the user
controls the direction and clock phase in which the loading
proceeds).
ADDRESSED CHANNEL LOADING:
When channel address (A0, A1, A2) = 000 through 101, the
video data is loaded into Channels 0 through 5. (STSQ/CS
functions as “Chip Selection” this case.)
INTERNALLY SEQUENCED LOADING:
When channel address = 111 the video data is loaded in a
sequence determined internally. The sequencing is initiated by
a pulse applied to STSQ/CS input. The count proceeds from
0 to 5 if R/
L
is LOW or from 5 to 0 if R/
L
is HIGH.
DAC TRANSFER FUNCTION
V
OUT
= VMID + VFS
×
(
1
– N
/1023
); if INV is HIGH,
V
OUT
= VMID – VFS
×
(
1
– N
/1023
); if INV is LOW
where
VFS
= 2
×
(VREFHI – VREFLO)
MAXIMUM OUTPUT VOLTAGE
The maximum output signal swing is constrained by the output
voltage compliance of the DACs and the output dynamic range
of the output amplifiers. The minimum voltage allowed at the
outputs of the DACs is about 6 V. This constrains the minimum
value of VMID to be 6 V. The output amplifiers will swing and
settle cleanly, as described on the specification page, for output
voltages within 1.5 V from each supply voltage rail.
For a given value of V
MID
, the voltage required to saturate the
video output voltages defines the maximum usable full-scale
voltage. For example, if VMID is less than AVCC/2, the maxi-
mum value of VFS is (VMID – 1.5 V). If VMID is greater than
AVCC/2, the maximum useful VFS is (AVCC – 1.5 – VMID).
Figure 1 graphically describes these limiting factors.
V
6
7.5
VMID – Volts
6
4.5
Figure 1. Valid Range for VMID with Respect to VFS
(AVCC = 15 V)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD8381 | Fast, High Voltage Drive, 6-Channel Output DecDriverTM Decimating LCD Panel Driver |
| AD8381AST | Fast, High Voltage Drive, 6-Channel Output DecDriverTM Decimating LCD Panel Driver |
| AD8381AST-REEL | Fast, High Voltage Drive, 6-Channel Output DecDriverTM Decimating LCD Panel Driver |
| AD8390 | Low Power, High Output Current Differential Amplifier |
| AD8390ACP-EVAL | Low Power, High Output Current Differential Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8380JSZ | 制造商:Analog Devices 功能描述:LCD DRVR 3.3V/5V/12V/15V/18V 44-Pin MQFP |
| AD8381 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fast, High Voltage Drive, 6-Channel Output DecDriverTM Decimating LCD Panel Driver |
| AD8381AST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fast, High Voltage Drive, 6-Channel Output DecDriverTM Decimating LCD Panel Driver |
| AD8381AST-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fast, High Voltage Drive, 6-Channel Output DecDriverTM Decimating LCD Panel Driver |
| AD8381-EB | 制造商:Analog Devices 功能描述:LCD DRVR 9 TO 18V - Bulk |
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