
REV. B
–2–
AD8380–SPECIFICATIONS
Model
VIDEO DC PERFORMANCE
1
VDE
VCME
Scale Factor Error
Offset Error
REFERENCE INPUTS
VMID Range
2
VMID Bias Current
VFS Range
VREFHI
VREFLO
VREFHI Input Resistance
VREFLO Bias Current
VREFHI Input Current
3
RESOLUTION
Coding
DIGITAL INPUT CHARACTERISTICS
Input Data Update Rate
Clock to Data Setup Times: t
1
Clock to STSQ Setup Times: t
3
Clock to XFR Setup Times: t
5
Maximum CLK Rise and Fall Time, t
7
Clock to A[0:2] Hold Times: t
9
Clock to Data Hold Times: t
2
Clock to STSQ Hold Times: t
4
Clock to XFR Hold Times: t
6
Clock to A[0:2] Setup Times: t
8
C
IN
I
IN
V
IH
V
IL
V
TH
VIDEO OUTPUT CHARACTERISTICS
Output Voltage Swing
CLK to VID Delay
4
Output Current
VIDEO OUTPUT DYNAMIC PERFORMANCE
(@ 25 C, AVCC = 15 V, DVCC = 3.3 V, T
MIN
= 0 C, T
MAX
= 85 C, unless
otherwise noted)
Conditions
Min
Typ
Max
Unit
T
MIN
to T
MAX
DAC Code = 450 to 800
DAC Code = 450 to 800
DAC Code = 0 to 1023
DAC Code = 0 to 1023
–7.5
–3.5
–0.25
–7
+1
+0.5
+7.5
+3.5
+0.25
+7
mV
mV
%
mV
+1
6
7
3
5
AVCC – 2.5
VREFHI – 2.5 VREFHI – 0.5
3.3
0.2
750
7.5
V
μ
A
V
V
V
k
μ
A
μ
A
VFS = 2
×
(VREFHI–VREFLO)
1
VREFLO +0.5
VMID – 0.5
6
AVCC
to VREFLO
VFS = 5 V
Binary
10
Bits
75
Ms/s
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
μ
A
V
V
V
1
1
1
4
4
4
4
4
1
3
0.6
2.0
0.8
Threshold Voltage
1.4
AVCC – V
OH
, V
OL
– AVEE
50% of VIDx
1.1
15.5
1.3
17.5
V
ns
mA
13.5
30
T
MIN
to T
MAX
, V
O
=
5 V Step,
C
L
= 150 pF, R
S
= 25
Data Switching Slew Rate
Invert Switching Slew Rate
Data Switching Settling Time to 1%
5
Data Switching Settling Time to 0.25%
Invert Switching Settling Time to 1%
5
Invert Switching Settling Time to 0.25%
CLK Feedthrough
6
All-Hostile Crosstalk
7
Amplitude
Glitch Duration
POWER SUPPLY
Supply Rejection (VDE)
DVCC, Operating Range
DVCC, Quiescent Current
AVCC, Operating Range
Total AVCC Quiescent Current
STBY AVCC Current
STBY DVCC Current
OPERATING TEMPERATURE RANGE
270
625
26
35
30
85
2
V/
μ
s
V/
μ
s
ns
ns
ns
ns
mV p-p
32
65
40
100
5
95
40
mV p-p
ns
+V
S
= 15 V
±
1 V
1
mV/V
V
mA
V
mA
mA
mA
°
C
3
5.5
35
24
44
5
5
85
22
9
33
0.5
0.1
STBY = H
STBY = H
0
NOTES
1
For definitions of VDE and VCME, see the Transfer Function section. Scale factor error is expressed as percentage of VFS.
2
See Figure 1 for valid ranges of VMID.
3
VREFHI Input Current = (VREFHI – VREFLO)/(VREFHI Input Resistance) = 2.5 V/3.3 k
.
4
Delay time from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV.
5
For best settling time results, use minimum series output resistance, R
of 25
.
6
An output channel is selected, and glitch is monitored as CLK is driven. STSQ and XFR are set to logic low.
7
Input data is loaded such that any five output channels change by VFS (i.e., 5 V), and the sixth unselected channel is monitored. Measurement is made for both states of INV.
Specifications subject to change without notice.