REV. 0
AD8369
–17–
310
12
49
8
7
611
5
2
13
1
15
22
24
16
21
20
19
18
23
17
14
25
D-SUB 25 PIN MALE
1nF
RL
1nF
9
10
11
12
13
14
15
16
PWUP VPOS SENB
FILT CMDC OPHI
INHI COMM
INLO
DENB
COMM BIT0
BIT1
BIT2
BIT3
AD8369
OPLO
C7
0.1 F
8
7
6
5
4
3
2
1
C5
0.1 F
IN
J1
IN
J2
TC4-1W
R1
0
T1
R2
0
C4
C3
OUT
J6
OUT
J7
TC4-1W
R12
0
R11
0
T2
C8
1nF
R5
OPEN
VS
PWUP
SW 2
PWDN
2
1
3
C8
1nF
R6
0
R7
0
R8
0
R9
0
R10
0
VS
A
B
1
14
SW3
SW4
R3
1k
R13
1k
LATCH
CLOCK
DATA
R4
1k
C9
OPEN
34
6
7
10
912
25
8
11
28
4
SW1
1
2
3
C1
C2
Figure 9. Evaluation Board Schematic
Key considerations when laying out an RF trace with a controlled
impedance include:
Space the ground plane to either side of the signal trace at least
3 line-widths away to ensure that a microstrip (vertical dielec-
tric) line is formed, rather than a coplanar (lateral dielectric)
waveguide.
Ensure that the width of the microstrip line is constant and
that there are as few discontinuations (component pads, etc.)
as possible along the length of the line. Width variations
cause impedance discontinuities in the line and may result
in unwanted reflections.
Do not use silkscreen over the signal line; this will alter the
line impedance.
Keep the length of the input and output connection lines as
short as possible.
3W
W
H
T
r
Figure 8. Cross-Sectional View of a PC Board
The AD8369 contains both digital and analog sections. Care
should be taken to ensure that the digital and analog sections
are adequately isolated on the PC board. The use of separate
ground planes for each section connected at only one point via a
ferrite bead inductor will ensure that the digital pulses do not
adversely affect the analog section of the AD8369.