(VS = 5 V, T = 25 C, RS " />
參數(shù)資料
型號(hào): AD8369ARUZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 12/24頁(yè)
文件大?。?/td> 0K
描述: IC AMP VGA 16TSSOP
標(biāo)準(zhǔn)包裝: 96
系列: X-AMP®
放大器類型: 可變?cè)鲆?br>
電路數(shù): 1
轉(zhuǎn)換速率: 1200 V/µs
-3db帶寬: 600MHz
電流 - 輸入偏壓: 160µA
電流 - 電源: 37mA
電壓 - 電源,單路/雙路(±): 3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 775 (CN2011-ZH PDF)
REV. 0
–2–
AD8369–SPECIFICATIONS
(VS = 5 V, T = 25 C, RS = 200
, RL = 1000
, Frequency = 70 MHz, at maximum gain,
unless otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Unit
OVERALL FUNCTION
Frequency Range
3 dB Bandwidth
LF
*
600
MHz
GAIN CONTROL INTERFACE
Voltage Gain Span
45
dB
Maximum Gain
All bits high (1 1 1 1)
40
dB
Minimum Gain
All bits low (0 0 0 0)
–5
dB
Gain Step Size
3dB
Gain Step Accuracy
Over entire gain range, with respect to 3 dB step
±0.05
dB
Gain Step Response Time
Step = 3 dB, settling to 10% of final value
30
ns
INPUT STAGE
Input Resistance
From INHI to INLO
200
W
From INHI to COMM, from INLO to COMM
100
W
Input Capacitance
From INHI to INLO
0.1
pF
From INHI to COMM, from INLO to COMM
1.1
pF
Input Noise Spectral Density
2
nV/
÷Hz
Input Common-Mode DC Voltage Measured at pin CMDC
1.7
V
Maximum Linear Input
|VINHI – VINLO| at Minimum Gain
2.2
V
OUTPUT STAGE
Output Resistance
From OPHI to OPLO
200
W
From OPHI to COMM, from OPLO to COMM
100
W
Output Capacitance
From OPHI to OPLO
0.25
pF
From OPHI to COMM, from OPLO to COMM
1.5
pF
Common-Mode DC Voltage
No input signal
VS/2
V
Slew Rate
Output step = 1 V
1200
V/
ms
POWER INTERFACE
Supply Voltage
3.0
5.5
V
Quiescent Current
PWUP high
37
42
mA
vs. Temperature
–40
∞C TA 85∞C52
mA
Disable Current
PWUP low
400
750
mA
vs. Temperature
–40
∞C TA 85∞C1
mA
POWER UP INTERFACE
Pin PWUP
Enable Threshold
1.0
V
Disable Threshold
2.2
V
Response Time
Time delay following low to high transition
7
ms
on PWUP until output settles to within 10%
of final value
Input Bias Current
PWUP = 5 V
160
mA
DIGITAL INTERFACE
Pins SENB, BIT0, BIT1, BIT2, BIT3,
and DENB
Low Condition
2.0
V
High Condition
3.0
V
Input Bias Current
Low input
150
mA
Frequency = 10 MHz
Voltage Gain
40.5
dB
Gain Flatness
Within
±10 MHz of 10 MHz
+0.05
*
dB
Noise Figure
7.0
dB
Output IP3
f1 = 9.945 MHz, f2 = 10.550 MHz
+22
dBV rms
+22
dBm
IMD3
f1 = 9.945 MHz, f2 = 10.550 MHz
VOPHI – VOPLO = 1 V p-p composite
–74
dBc
Harmonic Distortion
Second-Order, VOPHI – VOPLO = 1 V p-p
–72
dBc
Third-Order, VOPHI – VOPLO = 1 V p-p
–71
dBc
P1dB
For
±1dB deviation from linear gain
+3
dBV rms
+3
dBm
*The low frequency high-pass corner is determined by the capacitor on pin FILT, C FILT. See the Theory of Operation section for details.
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