參數(shù)資料
型號: AD8369ARUZ
廠商: Analog Devices Inc
文件頁數(shù): 19/24頁
文件大?。?/td> 0K
描述: IC AMP VGA 16TSSOP
標(biāo)準(zhǔn)包裝: 96
系列: X-AMP®
放大器類型: 可變增益
電路數(shù): 1
轉(zhuǎn)換速率: 1200 V/µs
-3db帶寬: 600MHz
電流 - 輸入偏壓: 160µA
電流 - 電源: 37mA
電壓 - 電源,單路/雙路(±): 3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
產(chǎn)品目錄頁面: 775 (CN2011-ZH PDF)
REV. 0
–4–
AD8369
Parameter
Conditions
Min
Typ
Max
Unit
Frequency = 380 MHz
Voltage Gain
38.5
dB
Gain Flatness
Within
±20 MHz of 380 MHz
±0.15
dB
Noise Figure
7.8
dB
Output IP3
f1 = 379.55 MHz, f2 = 380.45 MHz
+8.5
dBV rms
+8.5
dBm
IMD3
f1 = 379.55 MHz, f2 = 380.45 MHz,
VOPHI – VOPLO = 1 V p-p composite
–47
dBc
Harmonic Distortion
Second-Order, VOPHI – VOPLO = 1 V p-p
–45
dBc
Third-Order, VOPHI – VOPLO = 1 V p-p
–49
dBc
P1dB
For
±1 dB deviation from linear gain
+0.5
dBV rms
+0.5
dBm
Specifications subject to change without notice.
SPECIFICATIONS (Continued)
TIMING SPECIFICATIONS
SERIAL PROGRAMMING TIMING REQUIREMENTS
(VS = 5 V, T = 25
C)
Parameter
Typ
Unit
Minimum Clock Pulsewidth (TPW)10
ns
Minimum Clock Period (TCK)20
ns
Minimum Setup Time Data vs. Clock (TDS)2
ns
Minimum Setup Time Data Enable vs. Clock (TES)2
ns
Minimum Hold Time Clock vs. Data Enable (TEH)2
ns
Minimum Hold Time Data vs. Clock (TDH)4
ns
TCK
TPW
TEH
TES
CLOCK
DISABLED
CLOCK
DISABLED
CLOCK
ENABLED
DATA IS LATCHED ON LOW-TO-HIGH TRANSITION OF DENB
(NOT TO SCALE)
TDH
TDS
MSB
MSB–1
MSB–2
LSB
CLOCK
(BIT 1)
DATA
(BIT 0)
DATA
ENABLE
(DENB)
Serial Programming Timing
PARALLEL PROGRAMMING TIMING REQUIREMENTS
(VS = 5 V, T = 25
C)
Parameter
Typ
Unit
Minimum Setup Time Data Enable vs. Data (TES)2
ns
Minimum Hold Time Data Enable vs. Data (TEH)2
ns
Minimum Data Enable Width (TPW)4
ns
MSB
(BIT3)
DATA IS LATCHED ON HIGH-TO-LOW
TRANSITION OF DENB
DENB
TES
TEH
TPW
LSB
(BIT0)
MSB–2
(BIT1)
MSB–1
(BIT2)
(NOT TO SCALE)
Parallel Programming Timing
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