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參數(shù)資料
| 型號(hào)： | AD8330 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Cost DC-150 MHz Variable Gain Amplifier |
| 中文描述： | 低成本DC - 150 MHz的可變增益放大器 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 681K |
| 代理商： | AD8330 |
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REV. A
AD8330
–21–
1.2
1.0
0.8
0.6
0.4
0.2
0
5ns
10ns
15ns
25ns
20ns
0
–0.2
0.2
–0.4
–0.6
–1.0
–1.2
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
0
–0.2
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
Figure 19. Typical Pulse Responses for Figure 18
Figure 19 shows typical results for V
DBS
= 0.24 V, a square wave
input amplitude of 450 mV (the actual combination is not impor-
tant) and a rise time of 2 ns. V
MAG
raised to 2.0 V is used. In the
upper waveforms the load capacitors are both zero, and a small
amount of overshoot is visible; with 40 pF the response is cleaner.
A shunt capacitance of 20 pF from OPHI to OPLO will have a
similar effect. Coupling capacitors for this demonstration are
sufficiently large to prevent any visible droop over this time scale.
The outputs at the load side will eventually assume a mean value
of zero, with negative and positive excursions depending on the
duty-cycle.
The bandwidth from pin VMAG to these outputs is somewhat
higher than that from the normal input pins. Thus when this pin
is used to rapidly modulate the primary signal, some further
experimentation with response optimization may be required. In
general, the AD8330 is very tolerant of a wide range of loading
conditions.
Preserving Absolute Gain
Although the AD8330 is not laser-trimmed, its absolute gain cali-
bration, being based mainly on ratios, is very good. Full details can
be found in the Specifications and in the typical performance
curves. Nevertheless, having finite input and output impedances,
the gain is necessarily dependent on the source and load condi-
tions. The loss incurred when either of these is finite causes an
error in the absolute gain, which may also be uncertain due to
the approximately
±
20% tolerance in the absolute value of the
input and output impedances.
Often, such losses and uncertainties can be tolerated and accom-
modated by a correction to the gain control bias. On the other
hand, the error in the loss can be essentially nulled by using
appropriate modifications to either the source impedance (R
S
)
or the load impedance (R
L
), or both, in some cases by padding
them with series or shunt components.
The formulation for this correction technique was described
previously. However, to simplify its use, Table I is provided, showing
spot values for combinations of R
S
and R
L
resulting in an overall
loss that will not be dependent on sample-to-sample variations
in on-chip resistances. Furthermore, this fixed and predictable loss
can be corrected by an adjustment to V
MAG
, as indicated in Table 1.
Table I. Preserving Absolute Gain
Uncorrected LossV
MAG
Required
R
L
(
)
Factor
15k
0.980
10k
0.971
7.5k
0.961
5.0k
0.943
3.0k
0.907
2.0k
0.865
1.5k
0.826
1.0k
0.756
750
0.694
500
0.592
300
0.444
200
0.327
150
0.250
100
0.160
75
0.111
R
S
(
)
10
15
20
30
50
75
100
150
200
300
500
750
1k
1.5k
2k
dB
to Correct Loss
0.17
0.26
0.34
0.51
0.85
1.26
1.66
2.43
3.17
4.56
7.04
9.72
12.0
15.9
19.1
0.510
0.515
0.520
0.530
0.551
0.578
0.605
0.661
0.720
0.845
1.125
1.531
2.000
3.125
4.500
Calculation of Noise Figure
The AD8330 noise is a consequence of its intrinsic voltage-noise-
spectral-density (
E
NSD
) and the current-noise-spectral-density
(
I
NSD
). Their combined effect generates a net input noise,
V
NOISE_IN
,
which is a function of the device
’
s input resistance,
R
I
, nominally
1 k
, and the differential source resistance,
R
S
, as follows:
{
Note that we assume purely resistive source and input impedances
as a concession to simplicity. A more thorough treatment of noise
mechanisms, for the case where the source is reactive, is beyond the
scope of these brief notes. Also note that V
NOISE_IN
is the voltage-
noise-spectral-density appearing across the differential input pins,
INHI, INLO. In preparing for the calculation of noise figure,
we will define
V
SIG
as the open-circuit signal voltage across the
source and
V
IN
as the differential input to the AD8330. The
relationship is simply
V
R
R
R
I
S
At maximum gain, E
NSD
is 4.1 nV/
√
Hz
, and I
NSD
is 3 pA/
√
Hz
.
Thus, the short-circuit voltage noise is:
(
V
NOISE_IN
=
+
+
(
)
}
E
I
R
R
NSD
NSD
I
S
2
2
2
(16)
V
IN
=
+
(
)
SIG
I
(17)
V
NOISE_IN
=
)
+
(
)
+
k
(
)
4 1
.
3
1
0
2
2
2
/
/
nV
Hz
pA
Hz
=
5 08
.
/
nV
Hz
(18)
Next, examine the net noise when R
S
= R
I
= 1 k
, often incorrectly
called the
“
matching
”
condition, rather than
“
source impedance
termination,
”
which is the actual situation in this case. Repeating
the procedure:
V
NOISE_IN
=
(
)
+
(
)
+
k
(
)
4 1
.
3
1
1
2
2
2
/
/
nV
Hz
pA
Hz
k
≈
7 3
/
nV
Hz
(19)
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