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參數(shù)資料
| 型號： | AD8330 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Cost DC-150 MHz Variable Gain Amplifier |
| 中文描述： | 低成本DC - 150 MHz的可變增益放大器 |
| 文件頁數(shù)： | 2/28頁 |
| 文件大?。?/td> | 681K |
| 代理商： | AD8330 |
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REV. A
–2–
AD8330–SPECIFICATIONS
(V
S
= 5 V, T
= 25 C, C
= 12 pF on OPHI and OPLO, R
= 0/C, V
= 0.75 V, V
MODE
= HI,
V
MAG
= 0/C, V
OFST
= 0 V, Differential Operation, unless otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Unit
INPUT INTERFACE
Full-Scale Input
Pins INHI, INLO
V
DBS
= 0 V, Differential Drive
V
DBS
= 1.5 V
Pin-to-Pin
Either Pin to COMM
f = 1 MHz, V
DBS
= 1.5 V;
Inputs AC-shorted
±
1.4
±
4.5
800
±
2
±
6.3
1K
4
5
V
mV
pF
nV/
√
Hz
Input Resistance
Input Capacitance
Voltage Noise Spectral Density
1.2K
Common-Mode Voltage Level
Input Offset
Drift
Permissible CM Range
1
Common-Mode AC Rejection
3.0
1
2
V
mV rms
μ
V/
°
C
V
dB
dB
Pin OFST Connected to COMM
0
V
S
f = 1 MHz, 0.1 V rms
f = 50 MHz
–
60
–
55
OUTPUT INTERFACE
Small Signal
–
3dB Bandwidth
Peak Slew Rate
Peak-to-Peak Output Swing
Pins OPHI, OPLO
0 V < V
DBS
< 1.5 V
V
DBS
= 0
150
1500
±
2
±
4.5
2.5
62
150
–
62
–
53
MHz
V/
μ
s
V
V
V
nV/
√
Hz
dBc
dBc
±
1.8
±
4
2.4
±
2.2
V
MAG
≥
2 V (Peaks are Supply Limited)
Pin CNTR O/C
f = 1 MHz, V
DBS
= 0
Pin-to-Pin
V
OUT
= 1 V p-p, f = 10 MHz, R
L
= 1 k
V
OUT
= 1 V p-p, f = 10 MHz, R
L
= 1 k
Pin OFST
C
HPF
on Pin OFST (0 V< V
DBS
< 1.5 V)
C
HPF
= 3.3 nF, from OFST
to CNTR (Scales as 1/C
HPF
)
Pin CNTR
Common-Mode Voltage
Voltage Noise Spectral Density
Differential Output Impedance
HD2
2
HD3
2
2.6
120
180
OUTPUT OFFSET CONTROL
AC-Coupled Offset
High-Pass Corner Frequency
10
100
mV rms
kHz
COMMON-MODE CONTROL
Usable Voltage Range
Input Resistance
0.5
4.5
V
k
From Pin CNTR to V
S
/2
Pins VDBS, CMGN, MODE
CMGN Connected to COMM
CMGN O/C (V
CMGN
Rises to 0.2 V)
Mode HIGH or LOW
0.3 V
≤
V
DBS
≤
1.2 V
V
DBS
= 0
Flows out of pin VDBS
4
DECIBEL GAIN CONTROL
Normal Voltage Range
Elevated Range
Gain Scaling
Gain Linearity Error
Absolute Gain Error
Bias Current
Incremental Resistance
Gain Settling Time to 0.5 dB error
0 to 1.5
0.2 to 1.7
30
±
0.1
±
0.5
100
100
250
V
V
mV/dB
dB
dB
nA
M
ns
27
–
0.35
–
2
33
+0.35
+2
V
DBS
Stepped from 0.05 V
–
1.45 V
or 1.45 V
–
0.05 V
Pin MODE
Gain Increases with V
DBS
, MODE = O/C
Gain Decreases with V
DBS
Pins VMAG, CMGN
See Circuit Description Section
Gain is Nominal when V
MAG
= 0.5 V
Mode Up/Down
Mode Up Logic Level
Mode Down Logic Level
1.5
V
V
0.5
LINEAR GAIN INTERFACE
Peak Output Scaling, Gain vs. V
MAG
Gain Multiplication Factor vs. V
MAG
Usable Input Range
Default Voltage
Incremental Resistance
Bandwidth
3.8
4.0
4.2
V/V
2
0
0.48
5
0.52
V
V
k
MHz
V
MAG
O/C
0.5
4
150
For V
MAG
≥
0.1 V
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