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參數(shù)資料
| 型號： | AD8330 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Cost DC-150 MHz Variable Gain Amplifier |
| 中文描述： | 低成本DC - 150 MHz的可變增益放大器 |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 681K |
| 代理商： | AD8330 |
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REV. A
AD8330
–19–
single-sided extra attention may be needed to the decoupling on pin
VPSI, while if the output is loaded on only one of its two output
pins, this may require care in decoupling the VPSO pin. The
general common COMM and the output stage common CMOP
are usually grounded as shown in the figure; however, the Applica-
tions section shows how a negative supply can optionally be used.
The AD8330 is enabled by taking the ENBL pin to a logical high
(or, in all cases, the supply). The
“
UP
”
gain mode is enabled
either by leaving the MODE pin unconnected or taken to a
logical HI; when the opposite gain direction is needed, this pin
should be grounded or driven to a logical low. The low-pass
corner of the offset loop is determined by the capacitor CHPF;
this is preferably tied to the CNTR pin, which in turn should be
decoupled to ground. The gain-interface common pin CMGN
is grounded, and the output magnitude control pin V
MAG
is left
unconnected, or may optionally be connected to a 500 mV source
for basic gain calibration.
Connections to the input and output pins are not shown in this
figure because of the many options that are available. When the
AD8330 is used to drive an ADC, pins OPHI and OPLO may be
connected directly to the differential inputs of a suitable converter,
such as an AD9214. If an adjustment is needed to this common-
mode level, it can be introduced by applying that voltage to CNTR,
or, more simply, by using a resistor from this pin to either ground
or the supply (see APPLICATIONS). This pin can also supply the
common-mode voltage to an ADC that supports such a feature.
When the loads to be driven introduce a dc resistive path to
ground, coupling capacitors must be used; these should be of
sufficient value to pass the lowest frequency components of the
signal without excessive attenuation. Keep in mind that the voltage
swing on such loads will alternate both above and below ground,
requiring that the subsequent component must be able to cope
with negative signal excursions.
Gain and Swing Adjustments When Loaded
The output can also be coupled to a load via a transformer, in
which case it may be possible to achieve a higher load power by
impedance transformation. For example, using a 2:1 turns ratio,
a 50
final load will present a 200
load on the output. The gain
loss (relative to the basic value with no termination) will be
20 log
10
{(200+150)/200} or 4.86 dB, which can be restored by
raising the voltage on the V
MAG
pin by a factor of 10
4.86/20
or
1.75, from its basic value of 0.5 V to 0.875 V. This also restores
the peak swing at the 200
level to
±
2 V, or
±
1 V into the 50
final load.
Whenever a stable supply voltage is available, the additional voltage
may be provided simply by adding a resistor from this pin to the
supply. The calculation is based on knowing that the internal bias
is delivered via a 5 k
source; since an additional 0.375 V is
needed, the current in this external resistor must be 0.375 V/5 k
= 75
μ
A. Thus, using a 5 V supply, a resistor of 5 V
–
0.875 V/75
μ
A
= 55 k
would be used. Based on this example, the corrections
for other load conditions should be easy to calculate. If the effects
on gain and peak output swing due to supply variations cannot
be tolerated, VMAG must be driven by an accurate voltage.
Input Coupling
The dc common-mode voltage at the input pins varies with the
supply, the basic gain bias and temperature (see Figure 12); for
this reason, many applications will need to use coupling capacitors
from the source, which should be large enough to support the
lowest frequencies to be transmitted. Using one capacitor at
each input pin, their minimum value can be readily found from
this expression:
μ
320
C
IN
CPL
HPF
F
f
_
=
(15)
where f
HPF
is the
–
3dB frequency expressed in hertz. Thus, for
an f
HPF
of 10 kHz, 33 nF capacitors would be used.
It may occasionally be possible to avoid the use of coupling
capacitors, when the dc level of the driving source is within a certain
range, as shown in Figure 13. This range extends from 3.5 V to
4.5 V when using a 5 V supply, and at high basic gains, where the
effect of an incorrect dc level would be most troublesome, caus-
ing an increase in noise level due to internal aspects of the input
stage. For example, suppose the driver IC is an LNA having an
output topology in which its load resistors are taken to the supply,
and the output is buffered by emitter-followers. This presents a
source for the AD8330 that could readily be directly coupled.
DC-Coupled Signal Path
In many cases, where the VGA is not required to provide its lowest
noise, the full common-mode input range of zero to V
S
may be
used without problems, avoiding the need for any ac coupling
means. However, such direct coupling at both the input and output
will not automatically result in a fully dc-coupled signal path.
The internal offset compensation loop must also be disengaged,
by connecting the OFST pin to ground. Keep in mind that at the
maximum basic gain of 50 dB ( 316), every millivolt of offset at
the input, arising from whatever source, causes an output offset of
316 mV, which is an appreciable fraction of the peak output swing.
Since the offset correction loop is placed after the front-end
variable-gain sections of the AD8330, the most effective way of deal-
ing with such offsets is at the input pins, as shown in Figure 15.
For example, assume, for illustrative purposes, that the resistances
associated with each side of the source in a certain application
are 50
. If this source has a very low (op amp) output imped-
ance, the extra resistors should be inserted, with a negligible
noise penalty and an attenuation of only 0.83 dB. The resistor
values shown provide a trim range of about
±
2 mV.
COMM
OPHI
INLO
OPLO
INHI
VPSI
VPSO
CMOP
MODE
VDBS
CMGN
VMAG
OFST
ENBL
CNTR
VPOS
BIAS AND
V-REF
GAIN INTERFACE
CM MODE AND
OFFSET CONTROL
OUTPUT
STAGES
OUTPUT
CONTROL
VGA CORE
OUTPUT,
2V MAX
NC
BASIC GAIN BIAS
V
DBS:
0V TO 1.5V
RD1
CD2
CD1
CD3
RD2
50k
75k
R
ASSUMED
TO BE 50
ON EACH
SIDE
GROUND
V
S
2.7V–6V
Figure 15. Input Offset Nulling in a DC-Coupled System
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