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參數(shù)資料
| 型號： | AD8192ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SW MUX HDMI/DVI 2:1 56LFCSP |
| 標準包裝： | 1 |
| 功能： | 開關，DVI/HDMI |
| 電路： | 1 x 2:1 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 3.3V，5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 56-LFCSP-EP（8x8） |
| 包裝： | 托盤 |
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AD8192
Rev. 0 | Page 14 of 28
AUXILIARY MULTIPLEXER
The auxiliary (low speed) lines provide switching and buffering
for the DDC bus and buffering for the CEC line. The DDC
buffers are bidirectional and fully support arbitration, clock
synchronization, and other relevant features of a standard mode
I2C bus. The CEC buffer is bidirectional and includes integrated
on-chip pull-up resistors.
The HPD lines going into the AD8192 are normally high
impedance but are pulled low for greater than 100 ms when
a channel switch occurs.
The user has the option of slaving the auxiliary line switch
select to the high speed switch select by programming the
AUX_LK bit of the auxiliary device register. This causes the
auxiliary input channel to switch automatically when the user
programs the HS_CH bit of the high speed modes register.
The unselected auxiliary inputs of the AD8192 are placed into a
high impedance mode when the device is powered up and the
DDC inputs of the AD8192 are high impedance when the
device is powered off. This prevents contention on the DDC bus,
enabling a design to include an EDID upstream of the AD8192.
DDC LOGIC LEVELS
The AD8192 supports the use of flexible (3.3 V, 5 V) logic levels
on the DDC bus. The logic level for the DDC_A and DDC_B
buses are set by the voltage on VREF_AB, and the logic level
for the DDC_COM bus is set by the voltage on VREF_COM.
For example, if the DDC_COM bus is using 5 V I2C, then the
VREF_COM power supply pin should be connected to a +5 V
power supply. If the DDC_AB buses are using 3.3 V I2C, then
the VREF_AB power supply pin should be connected to a
+3.3 V power supply.
INPUT/OUTPUT MAPPING CONTROL
The input/output mapping of the AD8192 is completely
programmable. This allows a designer to integrate the AD8192
into virtually any application without requiring the use of vias
on the TMDS traces in the PCB layout.
The user can independently control the input/output mapping
of the TMDS channels for both Source A and Source B by
programming the A[3:0]_HS_MAP[0:1] bits of the Source A
input/output mapping register and the B[3:0]_HS_MAP[0:1]
bits of the Source B input/output mapping register, respectively.
The user can independently control the polarity of the eight
input channels by programming the A_SG and B_SG bits of the
source sign select register. This allows a designer to invert the
order of the p and n signals of a given TMDS pair inside the
AD8192 instead of on the PCB.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD8192ACPZ-RL7 | 功能描述:IC SW MUX HDMI/DVI 2:1 56LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關，多路復用器，多路分解器 系列:- 其它有關文件:STG4159 View All Specifications 標準包裝:5,000 系列:- 功能:開關 電路:1 x SPDT 導通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應商設備封裝:7-覆晶 包裝:帶卷 (TR) |
| AD8192-EVALZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:2:1 HDMI/DVI Switch with Equalization and DDC/CEC Buffers |
| AD8192XCPZ | 功能描述:IC SW MUX HDMI/DVI 2:1 56LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):上次購買時間 類型:視頻開關 應用:HDTV，投影儀，機頂盒 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商器件封裝:56-LFCSP-VQ（8x8） 標準包裝:1 |
| AD8192XCPZ-RL | 功能描述:IC SW MUX HDMI/DVI 2:1 56LFCSP 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):上次購買時間 類型:視頻開關 應用:HDTV，投影儀，機頂盒 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商器件封裝:56-LFCSP-VQ（8x8） 標準包裝:1 |
| AD8193 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Buffered 2:1 TMDS Switch |
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