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參數(shù)資料
| 型號(hào)： | AD8155ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/36頁 |
| 文件大小： | 0K |
| 描述： | IC MUX/DEMUX DUAL BUFFER 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | XStream™ |
| 功能： | 多路復(fù)用器/多路分解器 |
| 電路： | 2 x 2:1 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 1.6 V ~ 3.6 V |
| 電流 - 電源： | 735mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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AD8155
Rev. 0 | Page 30 of 36
SUPPLY SEQUENCING
Ideally, all power supplies should be brought up to the appropri-
ate levels simultaneously (power supply requirements are set by
the supply limits in Table 1 and the absolute maximum ratings
listed in Table 3). In the event that the power supplies to the
AD8155 are brought up separately, the supply power-up sequence
is as follows: DVCC is powered first, followed by VCC, and lastly
VTTI and VTTO. The power-down sequence is reversed, with VTTI
and VTTO being powered off first.
VTTI and VTTO contain ESD protection diodes to the VCC power
current condition in these devices (ISUSTAINED < 64 mA), the VTTI
and VTTO supplies should be powered on after VCC and should
be powered off before VCC.
If the system power supplies have a high impedance in the
powered off state, then supply sequencing is not required
provided the following limits are observed:
Peak current from VTTI or VTTO to VCC < 200 mA
Sustained current from VTTI or VTTO to VCC < 64 mA
SINGLE SUPPLY vs. MULTIPLE SUPPLY
OPERATION
The AD8155 supports a flexible supply voltage of 1.8 V to 3.3 V.
For some dc-coupled links, 1.2 V or ground-referenced signaling
may be desired. In these cases, the AD8155 can be run with a
split supply configuration. An example is shown in Figure 47.
TX
RX
0V
VTTO
VCC
DVCC
50
VTTI
CML
AD8155
Z0
VEE = –3.3V (OR –1.8V)
VOH = 0mV
VOL = –400mV
Z0
+
–
MCU
MCU_VSS
TO AD8155
I2C_SDA
VEE
ADuM1250
MCU_VDD
DVCC
I2C_SCL
08
26
2-
04
8
Figure 47. Multiple Supply Operation
Table 21. Alternate Supply Configuration Examples
Signal Level
VCC, VTTI, VTTO
VEE
1.2 V CML
1.2 V
2.1 V ≤VEE ≤ 0.6 V
GND 400 mV diff
GND
3.3 V ≤VEE ≤ 1.8 V
The AD8155 control signals are always referenced between
DVCC and VEE and, when using a split supply configuration,
logic level-shift circuits should be used. The evaluation board
design shows the use of the Analog Devices, Inc., ADUM1250
I2C isolator and a level shifter to level-shift the SCL and SDA
signals (for information about the evaluation board, see the
Evaluation of DC-Coupled Links
When evaluating the AD8155 dc-coupled, note that most lab
equipment is ground referenced whereas the AD8155 high
speed I/O are connected by 50 Ω on-die termination resistors to
VTTI and VTTO. To interface the AD8155 to ground-referenced,
high speed instrumentation (for example, the 50 Ω inputs of a
high speed oscilloscope), it is necessary to level-shift the outputs by
either using a dc-blocking network or powering the AD8155
between ground and a negative supply.
For example, to evaluate 1.8 V dc-coupled transmitter perfor-
mance with a 50 Ω ground-referenced oscilloscope, use the
following supply configuration:
VCC = VTTO = VTTI = Ground
VEE = 1.8 V
Ground < DVCC < 1.5 V
INITIALIZATION SEQUENCE FOR LOW POWER
AND LOS_INT OPERATION
The following programming sequence is required to initialize
the device in a low power mode and to enable the LOS_INT:
set the reserved bits to Logic 1 in the RX and TX control
registers by writing the value 0x0C to the 0x40, 0x48, 0x80,
0x88, 0xC0, and 0xC8 registers.
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