參數(shù)資料
型號(hào)： AD8155ACPZ-R7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/36頁(yè)
文件大小： 0K
描述： IC MUX/DEMUX DUAL BUFFER 64LFCSP
標(biāo)準(zhǔn)包裝： 750
系列： XStream™
功能： 多路復(fù)用器/多路分解器
電路： 2 x 2:1
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 1.6 V ~ 3.6 V
電流 - 電源： 735mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
AD8155
Rev. 0 | Page 18 of 36
RECEIVERS
The AD8155 receivers incorporate 50 Ω on-chip termination,
ESD protection, and a multizero equalization function capable
of delivering up to 18 dB of boost at 4.25 GHz. The AD8155 can
compensate signal degradation at 6.5 Gbps from over 40 inches
of FR4 backplane trace. The receive path also incorporates a
loss-of-signal (LOS) function that squelches the associated
transmitter when the midband differential voltage falls below a
specified threshold value. Finally, the receivers implement a sign-
swapping option (P/N swap), which allows the user to invert the
sign of the input signal path and eliminates the need for board-
level crossovers in the receive channels.
Input Structure and Allowed Input Levels
The AD8155 tolerates an input common-mode range (meas-
ured with zero differential input) of
VEE + 0.6 V < VICM < VCC + 0.3 V
Typical supply configurations include, but are not limited to,
those listed in Table 9.
Table 9. Typical Input Supply Configurations
Configuration
DVCC
VCC
VTTI
Low VTTI, AC-Coupled Input
3.3 V 1.8 V
1.8 V
1.6 V
Single 1.8 V Supply
3.3 V 1.8 V
1.8 V
3.3 V Core
3.3 V
1.8 V
Single 3.3 V Supply
3.3 V
When dc-coupling with LVDS, CML, or ECL signals, it can be
advantageous to operate with split or negative supplies (see the
Applications Information section). In these applications, it is
necessary to observe the maximum voltage ratings between VCC
and VEE and to select supply voltages for VTTO and VTTI in the
range of VCC to VEE to avoid activating the ESD protection
devices.
RP
52
RN
52
R1
750
R2
750
R3
1k
RLP
RL
Q1
Q2
RLN
RL
I1
VCC
VTTI
IP_xx
IN_xx
VEE
0
82
62
-03
8
Figure 37. Simplified Receiver Input Structure
Equalizer Settings
Every input lane offers a low power, asynchronous, programma-
ble receive equalizer for NRZ data up to 6.5 Gbps. The pin control
interface allows two levels of receive equalization. Register-based
control allows the user 10 equalizer settings. Register and pin
control boost settings are listed in Table 10. Equalization capa-
bility and resulting jitter performance are illustrated in Figure 30,
Figure 31, and Figure 34. Figure 34 shows the loss characteristic
of various reference channels, and Figure 30 and Figure 31 show
resulting DJ and RJ performance vs. equalizer setting against these
channels.
The two LSBs of Register 0x41, Register 0x81, and Register 0xC1
allow programming of all the equalizers in a port simultane-
ously (see Table 13). The 0x42, 0x82, and 0xC2 registers allow
per-lane programming of the equalizers (see Table 22). Be
aware that writing to the port-level equalizer registers updates
and overwrites per-lane settings.
Table 10. Equalizer Settings
Equalization Boost (dB)
EQ Register Setting
EQ Pin
0
2
1
N/A
4
2
N/A
6
3
N/A
8
4
1
10
5
N/A
12
6
N/A
14
7
N/A
16
8
N/A
18
9
N/A
RP
RTERM
RN
RTERM
ON-CHIP TERMINATION
ESD
LOSS
OF
SIGNAL
DETECT
EQUALIZER
VTHRESH
SIG
EQ OUT
VCC
VTTI
IP_xx
IN_xx
VEE
82
62
-037
0
Figure 38. Functional Diagram of the AD8155 Receiver
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