參數(shù)資料
型號(hào)： AD8134ACPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 0K
描述： IC OPAMP DIFF TRPL LDIST 24LFCSP
標(biāo)準(zhǔn)包裝： 1
放大器類型： 差分
電路數(shù)： 3
輸出類型： 差分
轉(zhuǎn)換速率： 1600 V/µs
-3db帶寬： 450MHz
電流 - 輸入偏壓： 67µA
電壓 - 輸入偏移： 4000µV
電流 - 電源： 31mA
電流 - 輸出 / 通道： 90mA
電壓 - 電源，單路/雙路(±)： 4.5 V ~ 12 V，±2.25 V ~ 6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 24-LFCSP-VQ（4x4）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： AD8134ACPZ-REEL7DKR
AD8134
Rev. A | Page 13 of 20
CALCULATING AN APPLICATION CIRCUIT’S INPUT
IMPEDANCE
The effective input impedance of a circuit such as that in
Figure 30 at VIP and VIN depends on whether the amplifier is
being driven by a single-ended or differential signal source. For
balanced differential input signals, the differential input
impedance, RIN, dm, between the inputs VIP and VIN is simply
RIN,dm = 2 × RG = 1.5 kΩ
In the case of a single-ended input signal (for example, if VIN is
grounded and the input signal is applied to VIP), the input
impedance becomes
()
k
125
.
1
2
1
=
+
×
=
F
G
F
G
IN
R
The circuit’s input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because
a fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor RG.
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
The inputs of the AD8134 are designed to facilitate level-
shifting of ground referenced input signals on a single power
supply. For a single-ended input, this would imply, for example,
that the voltage at VIN in Figure 30 would be 0 V when the
amplifier’s negative power supply voltage was also set to 0 V.
It is important to ensure that the common-mode voltage at the
amplifier inputs, VAP and VAN, stays within its specified range.
Since voltages VAP and VAN are driven to be essentially equal by
negative feedback, the amplifier’s input common-mode voltage
can be expressed as a single term, VACM. VACM can be calculated as
3
2
ICM
OCM
ACM
V
+
=
where VICM is the common-mode voltage of the input signal,
that is,
2
IN
IP
ICM
V
+
=
.
DRIVING A CAPACITIVE LOAD
A purely capacitive load can react with the output impedance
of the AD8134 to reduce phase margin, resulting in high
frequency ringing in the pulse response. The best way to
minimize this effect is to place a small resistor in series with
each of the amplifier’s outputs to buffer the load capacitance.
OUTPUT PULL-DOWN (OPD)
The AD8134 has an OPD pin that when pulled high
significantly reduces the power consumed while simultaneously
pulling the outputs to within less than 1 V of VS when used
with series diodes (see the Applications section). The equivalent
schematic of the output in the output pull-down state is shown
in Figure 31. (The ESD diodes shown in Figure 31 are for ESD
protection and are distinct from the series diodes used with the
output pull-down feature.) See Figure 18 and Figure 24 for the
output pull-down transient and isolation performance. The
threshold levels for the OPD input pin are referenced to the
positive power supply and are listed in the Specifications tables.
When the OPD pin is pulled high, the AD8134 enters the
output pull-down state.
VOUT
VCC
PULL-DOWN
(OUTPUT IS
PULLED DOWN
WHEN SWITCH
IS CLOSED)
VS–
VS+
ESD DIODE
04770-006
Figure 31. Output Pull-Down Equivalent Circuit
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