參數(shù)資料
型號(hào)： AD7986BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 18BIT 2MSPS SAR 20LFCSP
產(chǎn)品培訓(xùn)模塊： Motor Control
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 18
采樣率（每秒）： 2M
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 34mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 20-LFCSP-VQ
包裝： 托盤(pán)
輸入數(shù)目和類型： 1 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 780 (CN2011-ZH PDF)
AD7986
Rev. B | Page 19 of 28
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7986 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 25, and the corresponding timing is given in
With SDI tied to VIO, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. Once
a conversion is initiated, it continues until completion irrespective
of the state of CNV. This can be useful, for instance, to bring
CNV low to select other SPI devices, such as analog multiplexers;
however, CNV must be returned high before the minimum
conversion time elapses and then held high for the maximum
possible conversion time to avoid the generation of the busy
signal indicator. When the conversion is complete, the AD7986
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate, provided that it has an acceptable hold
time. After the 18th SCK falling edge or when CNV goes high
(whichever occurs first), SDO returns to high impedance.
AD7986
SDI
SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
VIO
07956-
018
Figure 25. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
ACQUISITION (n)
ACQUISITION
(n + 1)
ACQUISITION
(n - 1)
1
2
BEGIN DATA (n – 1)
CONVERSION (n)
END DATA (n – 1)
SCK
CNV
SDO
16
17
CONVERSION (n – 1)
END DATA (n – 2)
tCONV
tDATA
0
(I/O QUIET
TIME)
(I/O QUIET
TIME)
18
16
17
18
1
17
16
15
2
0
1
2
SDI = 1
>
tCONV
(QUIET
TIME)
tCYC
tACQ
tCNVH
tQUIET
tSCK
tDIS
tEN
tDSDO
tHSDO
tDATA
tCONV
07956-
116
Figure 26. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
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