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參數(shù)資料
| 型號： | AD7942BRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 250KSPS 10-MSOP |
| 標準包裝： | 50 |
| 系列： | PulSAR® |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
| 產(chǎn)品目錄頁面： | 780 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7942CB-ND - BOARD EVALUATION FOR AD7942 |
AD7942
Rev. B | Page 8 of
24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04
65
7-
00
4
AD7942
REF 1
VDD 2
IN+ 3
IN– 4
GND 5
VIO
10
SDI
9
SCK
8
SDO
7
CNV
6
NOTES
1. PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT
REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
REF
AI
Reference Input Voltage. The VREF range is from 0.5 V to VDD. REF is referred to the GND pin. Decouple REF
as closely as possible to a 10 μF capacitor.
2
VDD
P
Power Supply.
3
IN+
AI
Analog Input. IN+ is referred to IN. The voltage range, that is, the difference between IN+ and IN, is 0 V
to VREF.
4
IN
AI
Analog Input Ground Sense. Connect IN to the analog ground plane or to a remote sense ground.
5
GND
P
Power Supply Ground.
6
CNV
DI
Convert Input. This input pin has multiple functions. On its leading edge, CNV initiates the conversions
and selects the interface mode of the part: chain mode or CS mode. In CS mode, CNV enables the SDO pin
when low. In chain mode, the data should be read when CNV is high.
7
SDO
DO
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8
SCK
DI
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9
SDI
DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 14 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the busy
indicator feature is enabled.
10
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).
1 AI = analog input, DI = digital input, DO = digital output, and P = power.
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| AD7942BRMZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 250 kSPS PulSAR, Pseudo Differential ADC in MSOP/QFN |
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| AD7942BRMZ-RL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 250 kSPS PulSAR, Pseudo Differential ADC in MSOP/QFN |
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