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參數資料
| 型號： | AD7942BRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 250 kSPS PulSAR ADC in MSOP/QFN |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | MO-187BA, MSOP-10 |
| 文件頁數： | 5/28頁 |
| 文件大?。?/td> | 633K |
| 代理商： | AD7942BRM |
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Preliminary Technical Data
AD7942
Rev Pr B | Page 13 of 28
SW+
MSB
4,096C
IN+
LSB
COMP
CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
IN–
4C
2C
C
8,192C
SW–
MSB
4,096C
LSB
4C
2C
C
8,192C
Figure 20. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7942 is a fast, low power, single-supply, precise 14-bit
ADC using a successive approximation architecture.
The AD7942 is capable of converting 250,000 samples per
second (250 kSPS) and powers down between conversions.
When operating at 100 SPS, for example, it consumes typically
1.15W with a 2.5V supply, ideal for battery-powered
applications.
The AD7942 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7942 is specified from 2.3 V to 5.5 V, and can be
interfaced to either 5 V, 3.3 V, 2.5 V, or 1.8 V digital logic. It is
housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that
combines space savings and allows flexible configurations.
It is pin-for-pin-compatible with the 16 Bit ADC AD7685.
CONVERTER OPERATION
The AD7942 is a successive approximation ADC based on a
charge redistribution DAC. Figure 20 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 14 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN captured at the end of the acquisition
phase is applied to the comparator inputs, causing the
comparator to become unbalanced. By switching each element
of the capacitor array between GND and REF, the comparator
input varies by binary weighted voltage steps (VREF/2, VREF/4 . . .
VREF/16384). The control logic toggles these switches, starting
with the MSB, in order to bring the comparator back into a
balanced condition. After the completion of this process, the
part returns to the acquisition phase and the control logic
generates the ADC output code and a BUSY signal indicator.
Because the AD7942 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
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| AD7942BRMZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 250 kSPS PulSAR, Pseudo Differential ADC in MSOP/QFN |
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