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參數(shù)資料
| 型號： | AD7942BRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 250 kSPS PulSAR ADC in MSOP/QFN |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | MO-187BA, MSOP-10 |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 633K |
| 代理商： | AD7942BRM |
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Preliminary Technical Data
AD7942
Rev Pr B | Page 23 of 28
Chain Mode, No BUSY Indicator
This mode can be used to daisy chain multiple AD7942s on a 3-
wire serial interface. This feature is useful for reducing
component count and wiring connections, e.g., in isolated
multiconverter applications or for systems with a limited
interfacing capacity. Data readback is analogous to clocking a
shift register.
A connection diagram example using two AD7942s is shown in
Figure 37 and the corresponding timing is given in Figure 38.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the BUSY indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7942 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are then clocked by subsequent SCK falling edges.
For each ADC, SDI feeds the input of the internal shift register
and is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 14 × N clocks are required to
readback the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host also using the SCK falling edge will allow a faster
reading rate and, consequently more AD7942s in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate may be reduced due to the total
readback time. For instance, with a 5 ns digital host set-up time
and 3 V interface, up to six AD7942s running at a conversion
rate of 250 kSPS can be daisy-chained on a 3-wire port.
CNV
SCK
SDO
SDI
CLK
CONVERT
DATA IN
DIGITAL HOST
AD7942
B
CNV
SCK
SDO
SDI
AD7942
A
Figure 37. Chain Mode, No BUSY Indicator Connection Diagram
04656-P
rC-016
SDOA = SDIB
DA13
DA12
DA11
SCK
12
3
26
27
28
tSSDISCK
tHSDISC
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV
DA1
12
13
tSCK
tSCKL
tSCKH
DA0
15
16
14
SDIA = 0
SDOB
DB13
DB12
DB11
DA1
DB1DB0DA13
DA12
tHSDO
tDSDO
tSSCKCNV
tHSCKCNV
DA0
Figure 38. Chain Mode, No BUSY Indicator Serial Interface Timing
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