參數(shù)資料
型號(hào)： AD7942BRM
廠商： ANALOG DEVICES INC
元件分類(lèi)： ADC
英文描述： 14-Bit, 250 kSPS PulSAR ADC in MSOP/QFN
中文描述： 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10
封裝： MO-187BA, MSOP-10
文件頁(yè)數(shù)： 10/28頁(yè)
文件大?。?/td> 633K
代理商： AD7942BRM
AD7942
Preliminary Technical Data
Rev Pr B | Page 18 of 28
DIGITAL INTERFACE
Though the AD7942 has a reduced number of pins, it offers
flexibility in its serial interface modes.
The AD7942, when in CS mode, is compatible with SPI, QSPI,
digital hosts, and DSPs, e.g., Blackfin ADSP-BF53x or ADSP-
219x). This interface can use either 3-wire or 4-wire. A 3-wire
interface using the CNV, SCK, and SDO signals minimizes
wiring connections useful, for instance, in isolated applications.
A 4-wire interface using the SDI, CNV, SCK, and SDO signals
allows CNV, which initiates the conversions, to be independent
of the readback timing (SDI). This is useful in low jitter
sampling or simultaneous sampling applications.
The AD7942, when in chain mode, provides a daisy chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high and the chain mode is selected if SDI is low. The SDI
hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
In either mode, the AD7942 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a BUSY signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a BUSY indicator,
the user must time out the maximum conversion time prior to
readback.
The BUSY indicator feature is enabled as follows:
In the CS mode, if CNV or SDI is low when the ADC
conversion ends (Figure 32 and Figure 36).
In the chain mode, if SCK is high during the CNV rising edge
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