參數(shù)資料
型號： AD7939BCP
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
中文描述： 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, QCC32
封裝： MO-220-VHHD-2, LFCSP-32
文件頁數(shù)： 22/32頁
文件大小： 1332K
代理商： AD7939BCP
AD7938/AD7939
Preliminary Technical Data
Pseudo-Differential Mode
The AD7938/AD7939 can have four pseudo-differential pairs
(Pseudo Mode 1) or seven pseudo differential inputs (Pseudo
Mode 2) by setting the MODE0 and MODE1 bits in the control
register to 1, 0 and 1, 1, respectively. In the case of the four
pseudo-differential pairs, V
IN
+ is connected to the signal source
which must have an amplitude of V
REF
to make use of the full
dynamic range of the part. A dc input is applied to the V
IN
pin.
The voltage applied to this input provides an offset from ground
or a pseudo ground for the V
IN+
input. In the case of the seven
pseudo-differential inputs, the seven analog input signals inputs
are referred to a dc voltage applied to V
IN
7. The benefit of
pseudo-differential inputs is that they separate the analog input
signal ground from the ADC’s ground allowing dc common-
mode voltages to be cancelled. F
diagram for pseudo-differential mode.
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION
SET SEQ = SHDW = 0. SELECT THE DESIRED
CHANNEL TO CONVERT (ADD2 TO ADD0).
ISSUE CONVST PULSE TO INITIATE A CONVERSION
ON THE SELECTED CHANNEL.
INITIATE A READ CYCLE TO READ THE DATA
FROM THE SELECTED CHANNEL.
INITIATE A WRITE CYCLE TO SELECT THE NEXT
CHANNEL TO BE CONVERTED BY
CHANGING THE VALUES OF BITS ADD2 TO ADD0
IN THE CONTROL REGISTER. SEQ = SHDW = 0.
0
shows a connection
igure 32
Figure 32. Pseudo-Differential Mode Connection Diagram
V
IN+
V
IN–
V
REF
AD7938/
AD7939*
*ADDITIONAL PINS OMITTED FOR CLARITY
0
V
REF
p-p
0.47
μ
F
DC INPUT
VOLTAGE
ANALOG INPUT SELECTION
As shown in
configuration by setting the values in the MODE0 and MODE1
bits in the control register. Assuming the configuration has been
chosen, there are different ways of selecting the analog input to
be converted depending on the state of the SEQ and SHDW bits
in the control register.
Traditional Multichannel Operation (SEQ = SHDW = 0)
Any one of eight analog input channels or four pairs of channels
may be selected for conversion in any order by setting the SEQ
and SHDW bits in the control register to 0. The channel to be
converted is selected by writing to the address bits, ADD2 to
ADD0, in the control register to program the multiplexer prior
to the conversion. This mode of operation is of a traditional
multichannel ADC where each data write selects the next
channel for conversion. F
mode of operation. The channel configurations are shown in
.
, the user can set up their analog input
Table 9
Table 9
shows a flow chart of this
igure 33
Figure 33. Traditional Multichannel Operation Flow Chart
Using the Sequencer: Programmable Sequence (SEQ = 0,
SHDW = 1 )
The AD7938/AD7939 may be configured to automatically cycle
through a number of selected channels using the on-chip
programmable sequencer by setting SEQ = 0 and SHDW = 1 in
the control register. The analog input channels to be converted
are selected by setting the relevant bits in the shadow register to
1, see
.
Table 11
Once the shadow register has been programmed with the
required sequence, the next conversion executed is on the
lowest channel programmed in the SHDW register. The next
conversion executed will be on the next highest channel in the
sequence and so on. When the last channel in the sequence is
converted, the internal multiplexer returns to the first channel
selected in the shadow register and commences the sequence
again.
It is not necessary to write to the control register again once a
sequencer operation has been initiated. The WR input must be
kept high to ensure that the control register is not accidentally
overwritten or that a sequence operation is not interrupted. If
the control register is written to at any time during the
sequence, then ensure that the SEQ and SHDW bits are set to 1,
0 to avoid interrupting the conversion sequence. The sequence
program remains in force until such time as the
AD7938/AD7939 is written to and the SEQ and SHDW bits are
configured with any bit combination except 1, 0. F
shows a flow chart of the programmable sequence operation.
igure 34
Rev. PrN | Page 22 of 32
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