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參數(shù)資料
| 型號： | AD7939 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer |
| 中文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, QCC32 |
| 封裝： | MO-220-VHHD, LFCSP-32 |
| 文件頁數(shù)： | 9/32頁 |
| 文件大?。?/td> | 1332K |
| 代理商： | AD7939 |
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Preliminary Technical Data
AD7938/AD7939
PIN FUNCTION DESCRIPTION
0
D0
1
V
D
9
D
10
D
11
D
12
D
13
D
14
B
15
C
16
W
32
V
D
31
V
I
7
30
V
I
6
29
V
I
5
28
V
I
4
27
V
I
3
26
V
I
2
25
D1
2
D2
3
D3
4
D4
5
D5
6
D6
7
D7
8
V
IN
1
24
V
IN
0
23
V
REFIN
/V
REFOUT
22
AGND
21
20
19
WR
18
CONVST
17
AD7938/AD7939
TOP VIEW
(Not to Scale)
RD
CS
PIN 1
IDENTIFIER
Figure 2. Pin Configuration
Table 5. Pin Function Description
Pin
No
Mnemonic
1 to
8
Function
Data Bits 0 to 7. Three-state parallel digital I/O pins that provide the conversion result and also allow the control and
shadow registers to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels
for these pins are determined by the V
DRIVE
input. When reading from the AD7939, the two LSBs (DB0 and DB1) are
always 0 and the LSB of the conversion result is available on DB2.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the
AD7938/AD7939 operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at
V
DD
but should never exceed V
DD
by more than 0.3 V.
Digital Ground. This is the ground reference point for all digital circuitry on the AD7938/AD7939. This pin should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and
must not be more than 0.3 V apart, even on a transient basis.
Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled by CS
, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data
being written to or read from the AD7938/AD7939 is on DB0 to DB7. When HBEN is high, the top four bits of the data
being written to or read from the AD7938/AD7939 are on DB0 to DB3. When reading from the device, DB4 to DB6 of
the high byte will contain the ID of the channel for which the conversion result corresponds (see the channel address
bits in Table 9). When writing to the device, DB4 to DB7 of the high byte must be all 0s. Note that when reading from
the AD7939, the two LSBs of the low byte are 0s, and the remaining 6 bits, conversion data.
Data Bits 9 to 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the control and
shadow registers to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic high/low
voltage levels for these pins are determined by the V
DRIVE
input.
Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the falling
edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the result is
available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just prior to the
falling edge of BUSY on the 13
th
rising edge of SCLK, see Figure 38.
Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7938/AD7939 takes 13.5 clock cycles. The frequency of the master clock input therefore determines the
conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock.
Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track to
hold mode on the falling edge of CONVST and the conversion process is initiated at this point. Following power-down,
when operating in auto-shutdown or auto-standby modes, a rising edge on CONVST is used to power-up the device.
Write Input. Active low logic input used in conjunction with CS to write data to the internal registers.
Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion result
is placed on the data bus following the falling edge of RD read while CS is low.
Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data to
DB0 to DB7
9
V
DRIVE
10
DGND
11
DB8/HBEN
12
to
14
15
DB9 to
DB11
BUSY
16
CLKIN
17
CONVST
18
19
WR
RD
20
CS
Rev. PrN | Page 9 of 32
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