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參數(shù)資料
| 型號： | AD7939 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer |
| 中文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, QCC32 |
| 封裝： | MO-220-VHHD, LFCSP-32 |
| 文件頁數(shù)： | 30/32頁 |
| 文件大?。?/td> | 1332K |
| 代理商： | AD7939 |
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AD7938/AD7939
Preliminary Technical Data
slowed sufficiently when reading from and writing to the part to
require the insertion of one wait state. Extra wait states will be
necessary when using the TMS320C5x at their fastest clock
speeds (see the TMS320C5x User’s Guide for details).
Data is read from the ADC using the following instruction
IN D, ADC
where
D
is the data memory address and the
ADC
is the
AD7938/AD7939 address.
AD7938/
AD7939*
TMS32020/
TMS320C25/
TMS320C50*
WR
RD
DB11 TO DB0
DMD0 TO DMD15
A0 TO A15
IS
READY
INT
X
BUSY
CS
EN
CONVST
OPTIONAL
TMS320C25
ONLY
R/W
STRB
*ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS BUS
DATA BUS
ADDRESS
DECODER
0
MSC
Figure 47. Interfacing to the TMS32020/C25/C5x
AD7938/AD7939 to 80C186 Interface
Figure 48
shows the AD7938/AD7939 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer can
occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other
to store data. After the AD7938/AD7939 finish a conversion, the
BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA read
operation that also resets the interrupt latch. Sufficient priority
must be assigned to the DMA channel to ensure that the DMA
request is serviced before the completion of the next
conversion.
Figure 48. Interfacing to the 80C186
AD7938/
AD7939*
80C186*
WR
DB0 TO DB11
AD0 TO AD15
A16 TO A19
ALE
DRQ1
BUSY
CS
Q
R
S
CONVST
OPTIONAL
WR
RD
RD
*ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS/DATA BUS
ADDRESS BUS
DATA BUS
ADDRESS
LATCH
ADDRESS
DECODER
0
Rev. PrN | Page 30 of 32
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