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參數(shù)資料
| 型號： | AD7939 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer |
| 中文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, QCC32 |
| 封裝： | MO-220-VHHD, LFCSP-32 |
| 文件頁數(shù)： | 26/32頁 |
| 文件大小： | 1332K |
| 代理商： | AD7939 |
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AD7938/AD7939
Preliminary Technical Data
Reading Data from the AD7938/AD7939
With the W/B pin tied logic high, the AD7938/AD7939
interface operates in word mode. In this case, a single read
operation from the device accesses the conversion data-word on
Pins DB0 to DB11. The DB8/HBEN pin assumes its DB8
function. With the W/B pin tied to logic low, the
AD7938/AD7939 interface operates in byte mode. In this case,
the DB8/HBEN pin assumes its HBEN function. Conversion
data from the AD7938/ AD7939 must be accessed in two read
operations with 8 bits of data provided on DB0 to DB7 for each
of the read operations. The HBEN pin determines whether the
read operation accesses the high byte or the low byte of the12-
or 10-bit word. For a low byte read, DB0 to DB7 provide the
eight LSBs of the 12-bit word. For 10-bit operation, the two
LSBs of the low byte are 0s and are followed by 6 bits of
conversion data. For a high byte read, DB0 to DB4 provide the
four MSBs of the 12-/10-bit word. DB5 to DB7 of the high byte
provide the Channel ID. F
diagram for a 12-/10-bit transfer. When operated in word mode,
the HBEN input does not exist, and only the first read operation
shows the read cycle timing
is required to access data from the device. When operated in
byte mode, the two read cycles shown in F
to access the full data-word from the device.
are required
igure 38
igure 39
Figure 39. AD7938/AD7939 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/B = 0)
The CS and RD signals are gated internally and level triggered
active low. In either word mode or byte mode, CS and RD may
be tied together as the timing specifications for t
10
and t
11
are
0 ns minimum. This would mean the bus would be constantly
driven by the AD7938/AD7939.
The data is placed onto the data-bus a time t
13
after both CS and
RD go low. The RD rising edge can be used to latch data out of
the device. After a time, t
14
, the data lines will become three-
stated.
Alternatively, CS and RD can be tied permanently low and the
conversion data is valid and placed onto the data-bus a time, t
9
,
before the falling edge of BUSY.
t
11
t
10
t
13
t
15
t
15
t
16
t
16
t
14
t
12
t
17
LOW BYTE
HIGH BYTE
DB0 TO DB7
HBEN/DB8
RD
CS
0
Rev. PrN | Page 26 of 32
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