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參數(shù)資料
| 型號： | AD7927 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 8-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP |
| 中文描述： | 8通道，200 kSPS的，12位序列ADC的20引腳TSSOP |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 461K |
| 代理商： | AD7927 |
REV. 0
–6–
AD7927
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock
input is also used as the clock source for the AD7927s conversion process.
Data In. Logic input. Data to be written to the AD7927s Control Register is provided on this input
and is clocked into the register on the falling edge of SCLK (see the Control Register section).
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7927 and framing the serial data transfer.
Analog Ground. Ground reference point for all analog circuitry on the AD7927. All analog input
signals and any external reference signal should be referred to this AGND voltage. All AGND pins
should be connected together.
Analog Power Supply Input. The AV
DD
range for the AD7927 is from 2.7 V to 5.25 V. For the
0 V to 2
￥
REF
IN
range, AV
DD
should be from 4.75 V to 5.25 V.
Reference Input for the AD7927. An external reference must be applied to this input. The voltage
range for the external reference is 2.5 V
±
1% for specified performance.
Analog Input 0 through Analog Input 7. Eight single-ended analog input channels that are multiplexed
into the on-chip track-and-hold. The analog input channel to be converted is selected by using the
address bits ADD2 through ADD0 of the Control Register. The address bits in conjunction with the
SEQ and SHADOW bits allow the sequencer to be programmed. The input range for all input channels
can extend from 0 V to REF
IN
or 0 V to 2
￥
REF
IN
, as selected via the RANGE bit in the Control Register.
Any unused input channels should be connected to AGND to avoid noise pickup.
Data Out. Logic output. The conversion result from the AD7927 is provided on this output as a serial
data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the
AD7927 consists of two leading zeros, two address bits indicating which channel the conversion result
corresponds to, followed by the 12 bits of conversion data, MSB first. The output coding may be
selected as straight binary or twos complement via the CODING bit in the Control Register.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface
of the AD7927 will operate.
2
DIN
3
CS
4, 8, 17, 20
AGND
5, 6
AV
DD
7
REF
IN
16
–
9
V
IN
0
–
V
IN
7
18
DOUT
19
V
DRIVE
PIN CONFIGURATION
20-Lead TSSOP
1
AD7927
SCLK
AGND
20
TOP VIEW
(Not to Scale)
2
DIN
V
DRIVE
DOUT
19
3
CS
18
4
AGND
AGND
17
5
AV
DD
AV
DD
REF
IN
AGND
V
IN
0
V
IN
1
V
IN
2
V
IN
3
V
IN
4
V
IN
5
16
6
15
7
14
8
13
9
V
IN
7
V
IN
6
12
10
11
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