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參數(shù)資料
| 型號： | AD7884BQ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT SAMPLING HS 40-CDIP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 166k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 325mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-CDIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 40-Cerdip |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
REV. E
AD7884/AD7885
–13–
AD7884 to 80286 Interface
The 80286 is an advanced high performance processor with
special capabilities aimed at multiuser and multitasking systems.
Figure 19 shows an interface configuration for the AD7884 to
such a system. Note that only signals relevant to the AD7884
are shown. For the full 80286 configuration, refer to the iAPX
286 data sheet (Basic System Configuration).
In Figure 19 conversion is started by writing to a selected
address and causing
CS2 to go low. When conversion is complete,
BUSY goes high and initiates an interrupt. The processor can
then read the conversion result.
82288 BUS
CONTROLLER
MRDC
CLK
82284 CLOCK
GENERATOR
CLK
8282 OR
8283
LATCH
8286 OR 8287
TRANSCEIVER
DECODE
CIRCUITRY
8259A
INTERRUPT
CONTROLLER
CLK
D15–D0
A23–A0
AD7884
RD
CS
CONVST
DB15
DB0
BUSY
IR0–IR7
MEMORY READ
80286
CPU
CS1
CS2
Figure 19. AD7884 Interfacing to Basic iAPX 286 System
AD7885 to 8088 Interface
The AD7885, with its byte (8 + 8) data format, is ideal for use
with the 8088 microprocessor. Figure 20 is the interface diagram.
Conversion is started by enabling
CSA. At the end of conversion,
data is read into the processor. The read instructions are:
MOV AX, C001
Read 8 MSBs of data
MOV AX, C000
Read 8 LSBs of data
8088
AD7885
ADDRESS
DECODE LOGIC
CONVST
CS
RD
DB7–DB0
MN/
MX
DATA BUS
ADDRESS BUS
A15–A8
AD7–AD0
5V
A0
HBEN
RD
STB
8282
ALE
IO/
M
CSB
CSA
Figure 20. AD7885 to 8088 Interface
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