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參數(shù)資料
| 型號(hào)： | AD7884BQ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT SAMPLING HS 40-CDIP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 166k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 325mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-CDIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 40-Cerdip |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
REV. E
AD7884/AD7885
–7–
PIN FUNCTION DESCRIPTIONS
AD7884
AD7885
AD7885A
Description
VINV
This pin is connected to the inverting terminal of an op amp, as in Figure 6, and allows
the inversion of the supplied 3 V reference.
VREF–
This is the negative reference input and can be obtained by using an external amplifier to
invert the positive reference input. In this case, the amplifier output is connected to VREF–.
See Figure 6.
±3V
INS
±3V
INSThis is the analog input sense pin for the
±3 V analog input range on the AD7884 and
AD7885A.
±3V
INF
±3V
INFThis is the analog input force pin for the
±3 V analog input range on the AD7884 and
AD7885A. When using this input range, the
±5V
INF and
±5V
INS pins should be tied to
AGND.
±3V
IN
This is the analog input pin for the
±3 V analog input range on the AD7885. When using
this input range, the
±5VINF and ±5VINS pins should be tied to AGND.
±5V
INS
±5V
INS
±5V
INS
This is the analog input sense pin for the
±5 V analog input range on the AD7884, AD7885,
and AD7885A.
±5V
INF
±5V
INF
±5V
INF
This is the analog input force pin for the
±5 V analog input range on the AD7884, AD7885,
and AD7885A. When using this input range, the
±3VINF and ±3VINS pins should be tied
to AGND.
AGNDS
This is the ground return sense pin for the 9-bit ADC and the on-chip residue amplifier.
AGNDF
This is the ground return force pin for the 9-bit ADC and the on-chip residue amplifier.
AVDD
Positive analog power rail for the sample-and-hold amplifier and the residue amplifier.
AVSS
Negative analog power rail for the sample-and-hold amplifier and the residue amplifier.
GND
This is the ground return for the sample-and-hold section.
VSS
Negative Supply for the 9-Bit ADC
VDD
Positive Supply for the 9-Bit ADC and All Device Logic
CONVST
This asynchronous control input starts conversion.
CS
Chip Select Control Input
RD
Read Control Input. This is used in conjunction with
CS to read the conversion result
from the device output latch.
HBEN
High Byte Enable. Active high control input for the AD7885. It selects either the high or
the low byte of the conversion for reading.
BUSY
Busy Output. The
BUSY output goes low when the conversion begins and stays low until
it is completed, at which time it goes high.
DB0–DB15
16-Bit Parallel Data-Word Output on the AD7884
DB0–DB7
8-Bit Parallel Data Byte Output on the AD7885
DGND
Ground Return for All Device Logic
VREF+FVREF+FVREF+FReference Force Input
VREF+SVREF+SVREF+SReference Sense Input. The device operates from a 3 V reference.
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