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參數(shù)資料
| 型號： | AD7864ASZ-3 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT PAR 520K 4CH 44MQFP |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 520k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 120mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個差分，雙極 |
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AD7864
Rev. D | Page 16 of 28
logic high). The pointer is incremented to point to the next
register (next conversion result) when that conversion result is
available. Thus, FRSTDATA in Figure 9 is shown as going low
just prior to the second EOC pulse. Repeated read operations
during a conversion continue to access the data at the current
pointer location until the pointer is incremented at the end of
that conversion. Note that FRSTDATA has an indeterminate
logic state after initial power-up. This means that for the first
conversion sequence after power-up, the FRSTDATA logic
output may already be logic high before the end of the first
conversion (this condition is indicated by the dashed line in
). Also, the FRSTDATA logic output may already be
high as a result of the previous read sequence, as is the case after
the fourth read in
. The fourth read (rising edge of
RD)
resets the pointer to the first data location. Therefore, FRSTDATA
is already high when the next conversion sequence initiates. See
the
section.
Reading After the Conversion Sequence
this case, however, the results of the four conversions (on VIN1 to
VIN4) are read after all conversions have finished, that is, when
BUSY goes logic low. The FRSTDATA signal goes logic high at
the end of the first conversion just prior to EOC going logic low.
As mentioned previously, FRSTDATA has an indeterminate
state after initial power-up, therefore FRSTDATA may already
be logic high. Unlike the case when reading between each
conversion, the output data register pointer is incremented on
the rising edge of RD because the next conversion result is
available. This means FRSTDATA goes logic low after the first
rising edge on RD.
tBUSY
QUIET
TIME
t1
t8
t12
t3
t4
t5
t6
t7
VIN1
VIN2
VIN3
VIN4
100ns
DATA
CONVST
BUSY
EOC
FRSTDATA
RD
CS
H/S SEL
SL1 TO SL4
t2
tCONV
tACQ
t11
t10
01
34
1-
0
09
tCONV
Figure 9. Timing Diagram for Reading During Conversion
t10
t8
t4
t3
t6
t1
QUIET
TIME
DATA
CONVST
BUSY
EOC
FRSTDATA
RD
CS
VIN1
VIN2
VIN3
VIN4
VIN1
tBUSY
t2
t10
t7
0
13
41
-0
10
t3
Figure 10. Timing Diagram, Reading After the Conversion Sequence
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7864ASZ-32 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC |
| AD7864ASZ-3REEL | 功能描述:IC ADC 12BIT PAR 520K 4CH 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7864ASZ-3REEL2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC |
| AD7864BS-1 | 制造商:Analog Devices 功能描述:ADC Single SAR 520ksps 12-bit Parallel 44-Pin MQFP 制造商:Analog Devices 功能描述:IC 12-BIT ADC |
| AD7864BS-1REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 520ksps 12-bit Parallel 44-Pin MQFP T/R |
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