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參數(shù)資料
| 型號： | AD7864ASZ-3 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT PAR 520K 4CH 44MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 520k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 120mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個差分，雙極 |
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AD7864
Rev. D | Page 5 of 28
TIMING CHARACTERISTICS
VDRIVE = 5 V± 5%, AGND = DGND = 0 V, VREF = internal, clock = internal; all specifications TMIN to TMAX, unless otherwise noted.1, 2
Table 2.
Parameter
A, B Versions
Unit
Test Conditions/Comments
tCONV
1.65
μs max
Conversion time, internal clock
13
Clock cycles
Conversion time, external clock
2.6
μs max
CLKIN = 5 MHz
tACQ
0.34
μs max
Acquisition time
tBUSY
No. of channels ×
(tCONV + t9) t9
μs max
Selected number of channels multiplied by (tCONV + EOC pulse
width)—EOC pulse width
tWAKE-UP —External VREF
2
μs max
STBY rising edge to CONVST rising edge
6
ms max
STBY rising edge to CONVST rising edge
t1
35
ns min
CONVST pulse width
t2
70
ns max
CONVST rising edge to BUSY rising edge
READ OPERATION
t3
0
ns min
CS to RD setup time
t4
0
ns min
CS to RD hold time
t5
35
ns min
Read pulse width, VDRIVE = 5 V
40
ns min
Read pulse width, VDRIVE = 3 V
35
ns max
Data access time after falling edge of RD, VDRIVE = 5 V
40
ns max
Data access time after falling edge of RD, VDRIVE = 3 V
5
ns min
Bus relinquish time after rising edge of RD
30
ns max
t8
10
ns min
Time between consecutive reads
t9
75
ns min
EOC pulse width
180
ns max
t10
70
ns max
RD rising edge to FRSTDATA edge (rising or falling)
t11
15
ns max
EOC falling edge to FRSTDATA falling delay
t12
0
ns min
EOC to RD delay
WRITE OPERATION
t13
20
ns min
WR pulse width
t14
0
ns min
CS to WR setup time
t15
0
ns min
WR to CS hold time
t16
5
ns min
Input data setup time of rising edge of WR
t17
5
ns min
Input data hold time
1 Sample tested at initial release to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3 Refer to the Standby Mode Operation section. The maximum specification of 6 ms is valid when using a 0.1 μF decoupling capacitor on the VREF pin.
4 Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V.
5 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is
then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part, and as such, are independent of external bus loading capacitances.
TO
OUTPUT
50pF
1.6V
400A
1.6mA
01
34
1-
0
02
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD7864ASZ-32 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC |
| AD7864ASZ-3REEL | 功能描述:IC ADC 12BIT PAR 520K 4CH 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7864ASZ-3REEL2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC |
| AD7864BS-1 | 制造商:Analog Devices 功能描述:ADC Single SAR 520ksps 12-bit Parallel 44-Pin MQFP 制造商:Analog Devices 功能描述:IC 12-BIT ADC |
| AD7864BS-1REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 520ksps 12-bit Parallel 44-Pin MQFP T/R |
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