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參數(shù)資料
| 型號(hào)： | AD7829 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 8-Channel Sampling ADCs(2MSPS,8通道采樣8位A/D轉(zhuǎn)換器) |
| 中文描述： | 8通道采樣ADC（2MSPS，8通道采樣8位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 238K |
| 代理商： | AD7829 |
AD7822/AD7825/AD7829
–7–
REV. 0
Figures 2 and 3 below show simplified schematics of the ADC.
When the ADC starts a conversion, the track and hold goes into
hold mode and holds the analog input for 120 ns. T his is the
acquisition phase as shown in Figure 2, when Switch 2 is in
Position A. At the point when the track and hold returns to its
track mode, this signal is sampled by the sampling capacitor as
Switch 2 moves into Position B. T he first flash occurs at this
instant and is then followed by the second flash. T ypically, the
first flash is complete after 100 ns, i.e., at 220 ns, while the end
of the second flash and hence the 8-bit conversion result is
available at 330 ns. As shown in Figure 4, the track-and-hold
returns to track mode after 120 ns, and starts the next acquisi-
tion before the end of the current conversion. Figure 6 shows
the ADC transfer function.
CONTROL
LOGIC
REFERENCE
15
14
13
1
R1
HOLD
SAMPLING
CAPACITOR
A
B
SW2
R16
R15
R14
R13
LOGIC
OUTPUT
OUTPUT
D7
D6
D5
D4
D3
D2
D1
D0
V
IN
T/H 1
Figure 2. ADC Acquisition Phase
CONTROL
LOGIC
REFERENCE
15
14
13
1
R1
T/H
HOLD
SAMPLING
A
B
SW2
R16
R15
R14
R13
DECODE
LOGIC
OUTPUT
REGISTER
OUTPUT
DRIVERS
D7
D6
D5
D4
D3
D2
D1
D0
V
IN
Figure 3. ADC Conversion Phase
HOLD
HOLD
VALID DATA
120ns
CONVST
EOC
CS
RD
DB0-DB7
t
2
t
1
t
3
TRACK
TRACK
Figure 4. Track-and-Hold Timing
T Y PICAL CONNE CT ION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7822,
AD7825 and AD7829. T he AGND and DGND are connected
together at the device for good noise suppression. T he parallel
interface is implemented using an 8-bit data bus. T he end of
conversion signal (
EOC
) idles high, the falling edge of
CONVST
initiates a conversion and at the end of conversion the falling
edge of
EOC
is used to initiate an Interrupt Service Routine
(ISR) on a microprocessor. (See Parallel interface section for
more details.) V
REF
and V
MID
are connected to voltage source
such as the AD780, while V
DD
is connected to a voltage source
that can vary from 4.5 V to 5.5 V. (See T able I in Analog Input
section.) When V
DD
is first connected, the AD7822, AD7825 and
AD7829 power up in a low current mode, i.e., power-down, with
the default logic level on the
EOC
pin on the AD7822 and
AD7825 equal to a low. A rising edge on the
CONVST
pin will
cause the AD7829 to fully power up while a rising edge on the
PD
pin will cause the AD7822 and AD7825 to fully power up.
For applications where power consumption is of concern, the
automatic power-down at the end of a conversion should be
used to improve power performance. (See Power-Down Options
section of the data sheet.)
2.5V
AD780
SUPPLY
+4.5V TO +5.5V
10
m
F
0.1
m
F
V
DD
V
REF
V
MID
V
IN1
1.25V TO
3.75V INPUT
V
IN2
V
IN4(8)
AGND
DB0-DB7
EOC
RD
CS
CONVST
A0
A1
A2
PD
PARALLEL
INTERFACE
m
C/
m
P
AD7822/25/29
DGND
Figure 5. Typical Connection Diagram
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| AD7834AN | 2.35V-5.25V, 12 bit, 1MSPS, Serial ADC 6-SOT-23 -40 to 125 |
| AD7834AR | 2.35V-5.25V, 12 bit, 1MSPS, Serial ADC 6-SOT-23 -40 to 125 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7829-1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, 2 MSPS, 8-Bit, 8-Channel ADC |
| AD7829BN | 制造商:Analog Devices 功能描述:ADC Single Semiflash 2Msps 8-bit Parallel 28-Pin PDIP W 制造商:Rochester Electronics LLC 功能描述:8-CHNL 2MSPS PARALLEL 8-BIT ADC I.C. - Bulk 制造商:Analog Devices 功能描述:IC 8BIT ADC 7829 DIP28 |
| AD7829BNZ | 制造商:Analog Devices 功能描述:ADC Single Semiflash 2Msps 8-bit Parallel 28-Pin PDIP W 制造商:Analog Devices 功能描述:IC 8BIT ADC 7829 DIP28 |
| AD7829BNZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, 2 MSPS, 8-Bit, 1-/4-/8-Channel Sampling ADCs |
| AD7829BR | 制造商:Rochester Electronics LLC 功能描述:8-CHNL 2MSPS PARALLEL 8-BIT ADC I.C. - Bulk 制造商:Analog Devices 功能描述:IC 8-BIT ADC |
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