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參數(shù)資料
| 型號： | AD7819 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 8-Bit Sampling ADC(200kSPS,8位采樣A/D轉(zhuǎn)換器) |
| 中文描述： | 8位采樣ADC（速度高達(dá)200ksps，8位采樣的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 231K |
| 代理商： | AD7819 |
AD7819
–6–
REV. 0
CIRCUIT DESCRIPTION
Converter Operation
The AD7819 is a successive approximation analog-to-digital
converter based around a charge redistribution DAC. The ADC
can convert analog input signals in the range 0 V to V
DD
. Fig-
ures 2 and 3 below show simplified schematics of the ADC.
Figure 2 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A, the comparator is held in a
balanced condition and the sampling capacitor acquires the
signal on V
IN+
.
CHARGE
RESTRIBUTION
DAC
CONTROL
LOGIC
CLOCK
OSC
COMPARATOR
SW2
V
DD
/3
ACQUISITION
PHASE
SAMPLING
CAPACITOR
SW1
A
B
AGND
V
IN
Figure 2. ADC Track Phase
When the ADC starts a conversion, see Figure 3, SW2 will open
and SW1 will move to Position B causing the comparator to
become unbalanced. The Control Logic and the Charge Redis-
tribution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced the conversion is complete. The Control Logic generates
the ADC output code. Figure 7 shows the ADC transfer function.
CHARGE
RESTRIBUTION
DAC
CONTROL
LOGIC
CLOCK
OSC
COMPARATOR
SW2
V
DD
/3
CONVERSION
PHASE
SAMPLING
CAPACITOR
SW1
A
B
AGND
V
IN
Figure 3. ADC Conversion Phase
TYPICAL CONNECTION DIAGRAM
Figure 4 shows a typical connection diagram for the AD7819. The
parallel interface is implemented using an 8-bit data bus, the
falling edge of
CONVST
brings the BUSY signal high and at
the end of conversion, the falling edge of BUSY is used to
initiate an ISR on a microprocessor. (See Parallel Interface
section for more details.) V
REF
is connected to a well decoupled
V
DD
pin to provide an analog input range of 0 V to V
DD
. When
V
DD
is first connected the AD7819 powers up in a low current
mode, i.e., power down. A rising edge on the
CONVST
input
will cause the part to power up. (See Power-Up Times section.)
If power consumption is of concern, the automatic power-down
at the end of a conversion should be used to improve power
performance. See Power vs. Throughput Rate section of the
data sheet.
BUSY
RD
CS
CONVST
DB0-DB7
V
DD
V
REF
V
IN
GND
AD7819
m
C/
m
P
PARALLEL
INTERFACE
0V TO V
REF
INPUT
0.1
m
F
10
m
F
SUPPLY
+2.7V TO +5.5V
Figure 4. Typical Connection Diagram
Analog Input
Figure 5 shows an equivalent circuit of the analog input struc-
ture of the AD7819. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 200 mV. This will cause these diodes to become
forward biased and start conducting current into the substrate.
20 mA is the maximum current these diodes can conduct with-
out causing irreversible damage to the part. The capacitor C2 is
typically about 4 pF and can be primarily attributed to pin
capacitance. The resistor R1 is a lumped component made up
of the on resistance of a multiplexer and a switch. This resistor
is typically about 125
. The capacitor C1 is the ADC sampling
capacitor and has a capacitance of 3.5 pF.
V
DD
V
IN
C2
4pF
D1
D2
R1
125
C1
3.5pF
V
DD
/3
CONVERT PHASE – SWITCH OPEN
TRACK PHASE – SWITCH CLOSED
Figure 5. Equivalent Analog Input Circuit
DC Acquisition Time
The ADC starts a new acquisition phase at the end of a conver-
sion and ends on the falling edge of the
CONVST
signal. At the
end of a conversion there is a settling time associated with the
sampling circuit. This settling time lasts approximately 100 ns.
The analog signal on V
IN
is also being acquired during this set-
tling time. The minimum acquisition time needed is approxi-
mately 100 ns. Figure 6 shows the equivalent charging circuit
for the sampling capacitor when the ADC is in its acquisition
phase. R2 represents the source impedance of a buffer amplifier
or resistive network, R1 is an internal multiplexer resistance and
C1 is the sampling capacitor.
V
IN
R1
125
R2
C1
3.5pF
Figure 6. Equivalent Sampling Circuit
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