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參數(shù)資料
| 型號(hào)： | AD7819 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 8-Bit Sampling ADC(200kSPS,8位采樣A/D轉(zhuǎn)換器) |
| 中文描述： | 8位采樣ADC（速度高達(dá)200ksps，8位采樣的A / D轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 231K |
| 代理商： | AD7819 |
AD7819
–3–
REV. 0
TIMING CHARACTERISTICS
1, 2
Parameter
V
DD
= 3 V
6
10%
V
DD
= 5 V
6
10%
Units
Conditions/Comments
t
POWER-UP
t
1
t
2
t
3
t
4
t
5
t
63
t
73, 4
t
83
1
4.5
30
30
0
0
10
10
50
1
4.5
30
30
0
0
10
10
50
μ
s (max)
μ
s (max)
ns (min)
ns (max)
ns (min)
ns (min)
ns (max)
ns (max)
ns (min)
Power-Up Time of AD7819 after Rising Edge of
CONVST
.
Conversion Time.
CONVST
Pulse Width.
CONVST
Falling Edge to BUSY Rising Edge Delay.
CS
to
RD
Setup Time.
CS
Hold Time after
RD
High.
Data Access Time after
RD
Low.
Bus Relinquish Time after
RD
High.
Data Bus Relinquish to Falling Edge of
CONVST
Delay.
NOTES
1
Sample tested to ensure compliance.
2
See Figures 12, 13 and 14.
3
These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V
DD
= 5 V
±
10% and
0.4 V or 2 V for V
= 3 V
±
10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
7
, quoted in the Timing Characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
(–40
8
C to +125
8
C, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to DGND
(
CONVST
,
RD
,
CS
) . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Digital Output Voltage to DGND
(BUSY, DB0–DB7) . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
REF
IN
to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Analog Input . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Storage Temperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150
°
C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . +105
°
C/W
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . .+260
°
C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75
°
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215
°
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220
°
C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115
°
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215
°
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220
°
C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
≤
4 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
+1.6V
200μA
I
OL
200μA
I
OH
C
L
50pF
TO
OUTPUT
PIN
Figure 1. Load Circuit for Digital Output Timing
Specifications
ORDERING GUIDE
Linearity
Error
(LSB)
Package
Description
Package
Option
Model
AD7819YN
AD7819YR
AD7819YRU
±
1 LSB
±
1 LSB
±
1 LSB
Plastic DIP
Small Outline IC
Thin Shrink Small Outline RU-16
(TSSOP)
N-16
R-16A
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