參數(shù)資料
型號(hào)： AD7808BRZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 0K
描述： IC DAC 10BIT OCTAL SRL 24-SOIC
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 31
設(shè)置時(shí)間： 1.5µs
位數(shù)： 10
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 99mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 管件
輸出數(shù)目和類型： 8 電壓，雙極
采樣率（每秒）： 667k
產(chǎn)品目錄頁(yè)面： 785 (CN2011-ZH PDF)
AD7804/AD7805/AD7808/AD7809
–17–
REV. A
Table VII shows the twos complement transfer function for the
Sub DAC. Figure 23 shows the Sub DAC transfer function for
twos complement coding. Any Sub DAC output voltage can be
expressed as:
VOUT" = VBIAS/16
× (NB/256)
where NB is the decimal equivalent of the twos complement
input code. NB ranges from –128 to +127.
Table VII. Twos Complement Code Table for Sub DAC
Digital Input
Analog Input
MSB . . . LSB
01111111
(VBIAS/16)
× (127/256)
01111111
(VBIAS/16)
× (126/256)
00000001
(VBIAS/16)
× (1/256)
00000000
0
11111111
(–VBIAS/16)
× (1/256)
10000001
(–VBIAS/16)
× (127/256)
10000000
(–VBIAS/16)
× (128/256)
127
VBIAS
256
16
0
DAC
OUTPUT
VOLTAGE
128
VBIAS
256
16
80
81
DAC INPUT CODE
FF
00
01
7E
7F
Figure 23. Sub DAC Output Voltage vs. DAC Input Codes
(HEX) for Twos Complement Coding
The total output for a single channel when using twos comple-
ment coding is the sum of the voltage from the Main DAC and
the Sub DAC.
VOUT = VOUT' + VOUT"
= VBIAS + 1.875
× V
BIAS
× (NA/1024) + V
BIAS/16
× (NB/256)
= VBIAS
× (1 + 1.875 × NA/1024 + NB/4096)
where NA ranges from –512 to +511 and NB ranges from –128 to
+127. Figure 28 shows a pictorial view of the transfer function for
any DAC.
Configuring the AD7805/AD7809 for Twos Complement Coding
Figure 24 shows a typical configuration for the AD7805/AD7809.
The circuit can be used for either 3.3 V or 5 V operation and uses
the internal VDD/2 as the reference for the part and 10-bit paral-
lel interfacing is used. The following are the steps required to
operate the Main DACs in this part.
0.01 F
AD7805/
AD7809
AVDD
DVDD
VOUTA
VOUTB
VOUTC
VOUTD
AGND
DGND
LDAC
CLR
COMP
MODE
D9
D0
CS
WR
DVDD
REFIN
REFOUT
0.1 F
10 F
A1
A0
0.01 F
A2*
*USED ON THE
AD7809 ONLY
DIGITAL
INTERFACE
+3.3V/+5V
Figure 24. Typical Configuration for AD7805/AD7809
System Control Register Write:
MODE = 0, address inputs (A2, A1, A0) are don’t cares.
Write 020 Hex
Configure part for 10-bit parallel, twos
complement coding, normal operation
Channel Control Register Write:
MODE = 0, address inputs (A2, A1, A0) select desired channel.
Write 011 Hex
Internal VDD/2 selected as VBIAS for
DAC, and any DAC data writes that
follow are to the Main DAC.
DAC Data Register Write:
MODE = 1, address inputs (A2, A1, A0) select desired channel.
Write XXX Hex
With MODE = 1 all data writes are to
the selected DAC. XXX is the required
data. 200 Hex will give zero scale and 1FF
Hex will give full scale from the DAC.
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