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參數(shù)資料
| 型號(hào)： | AD7799 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power, 24-Bit/16-Bit Sigma-Delta ADC with In-Amp |
| 中文描述： | 低功耗，24-Bit/16-BitΣ-Δ型ADC在放大器 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大小： | 499K |
| 代理商： | AD7799 |
AD7798/AD7799
Preliminary Technical Data
TIMING CHARACTERISTICS
8, 9
Table 2. (AV
DD
= 2.7 V to 5.25 V; DV
DD
= 2.7 V to 5.25; GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV
DD
, unless otherwise
noted.)
Limit at T
MIN
, T
MAX
(B Version)
Unit
t
3
100
ns min
t
4
100
ns min
Read Operation
t
1
0
ns min
60
ns max
80
ns max
t
210
0
ns min
60
ns max
80
ns max
t
512, 13
10
ns min
80
ns max
t
6
100
ns max
t
7
10
ns min
Write Operation
t
8
0
ns min
t
9
30
ns min
t
10
25
ns min
t
11
0
ns min
8
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
9
See
and
.
Figure 3
Figure 4
and defined as the time required for the output to cross the V
OL
or V
OH
limits.
REV. PrD. Page 6 of 17
Parameter
Conditions/Comments
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Falling Edge to DOUT/RDY Active Time
DV
DD
= 4.75 V to 5.25 V
DV
DD
= 2.7 V to 3.6 V
SCLK Active Edge to Data Valid Delay
11
DV
DD
= 4.75 V to 5.25 V
DV
DD
= 2.7 V to 3.6 V
Bus Relinquish Time after CS Inactive Edge
SCLK Inactive Edge to CS Inactive Edge
SCLK Inactive Edge to DOUT/RDY High
CS Falling Edge to SCLK Active Edge Setup Time
11
Data Valid to SCLK Edge Setup Time
Data Valid to SCLK Edge Hold Time
CS Rising Edge to SCLK Edge Hold Time
10
These numbers are measured with the load circuit of
Figure 2
Figure 2
11
SCLK active edge is falling edge of SCLK.
12
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
.
The measured number is then
13
RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
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