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參數(shù)資料
| 型號(hào)： | AD7799 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power, 24-Bit/16-Bit Sigma-Delta ADC with In-Amp |
| 中文描述： | 低功耗，24-Bit/16-BitΣ-Δ型ADC在放大器 |
| 文件頁(yè)數(shù)： | 12/17頁(yè) |
| 文件大小： | 499K |
| 代理商： | AD7799 |
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AD7798/AD7799
Preliminary Technical Data
ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following
descriptions,
set
implies a Logic 1 state and
cleared
implies a Logic 0 state, unless otherwise stated.
REV. PrD. Page 12 of 17
COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0)
The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the com-
munications register. The data written to the communications register determines whether the next operation is a read or write operation,
and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected
register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of
the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications regis-
ter. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to
this default state by resetting the entire part. Table 5 outlines the bit designations for the communications register. CR0 through CR7 indi-
cate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in
brackets indicates the power-on/reset default status of that bit.
CR7
WEN(0)
Table 5. Communications Register Bit Designations
Bit Location
Bit Name
CR7
WEN
CR6
R/W(0)
CR5
RS2(0)
CR4
RS1(0)
CR3
RS0(0)
CR2
CREAD(0)
CR1
0(0)
CR0
0(0)
Description
Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually
occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay
at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits
will be loaded to the communications register.
A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this
position indicates that the next operation will be a read from the designated register.
Register Address Bits. These address bits are used to select which of the ADC’s registers are being
selected during this serial interface communication. See Table 6.
Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the
serial interface is configured so that the data register can be continuously read, i.e., the contents of the
data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The commu-
nications register does not have to be written to for data reads. To enable continuous read mode, the
instruction 01011100 must be written to the communications register. To exit the continuous read
mode, the instruction 01011000 must be written to the communications register while the RDY pin is
low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the
instruction to exit continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on
DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to
the device.
These bits must be programmed to logic 0 for correct operation.
CR6
R/W
CR5–CR3
RS2–RS0
CR2
CREAD
CR1–CR0
Table 6. Register Selection
RS2
RS1
0
0
0
0
0
0
0
1
0
1
0
RS0
0
0
1
0
1
Register
Status Register during a Read Operation
Mode Register
Configuration Register
Data Register
Register Size
8-Bit
8-Bit
16-Bit
16-Bit
24-Bit (AD7799)
16-bit (AD7798)
8-Bit
8-Bit
24-Bit (AD7799)
16-bit (AD7798)
24-Bit (AD7799)
16-Bit (AD7798)
1
1
1
0
0
1
0
1
0
ID Register
IO Register
Offset Register
1
1
1
Full-Scale Register
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