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參數(shù)資料
| 型號(hào)： | AD7799 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power, 24-Bit/16-Bit Sigma-Delta ADC with In-Amp |
| 中文描述： | 低功耗，24-Bit/16-BitΣ-Δ型ADC在放大器 |
| 文件頁(yè)數(shù)： | 14/17頁(yè) |
| 文件大?。?/td> | 499K |
| 代理商： | AD7799 |
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AD7798/AD7799
Preliminary Technical Data
Table 9. Operating Modes
MD2
MD1
0
0
REV. PrD. Page 14 of 17
MD0
0
Mode
Continuous Conversion Mode (Default).
In continuous conversion mode, the ADC continuously performs conversions and places the result in the data
register. RDY goes low when a conversion is complete. The user can read these conversions by placing the
device in continuous read mode whereby the conversions are automatically placed on the DOUT line when
SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to
the communications register. After power-on, or following a write to the Mode, Configuration or IO
Registers, a conversion is available after a period 2/ f
ADC
while subsequent conversions are available at a
frequency of f
ADC
.
Single Conversion Mode.
In single conversion mode, the ADC is placed in power-down mode when conversions are not being
performed. When single conversion mode is selected, the ADC powers up and performs a single conversion,
which occurs after a period 2/f
ADC
. The conversion result in placed in the data register, RDY goes low, and the
ADC returns to power-down mode. The conversion remains in the data register and RDY remains active (low)
until the data is read or another conversion is performed.
Idle Mode.
In Idle Mode, the ADC Filter an Modulator are held in a reset state although the modulator clocks are still
provided
Power-Down Mode.
In power down mode, all the AD7798/99 circuitry is powered down including the power switch and
burnout currents
.
Internal Zero-Scale Calibration.
An internal short is automatically connected to the enabled channel. A calibration takes 2 conversion cycles
to complete. RDY goes high when the calibration is initiated and returns low when the the calibration is
complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in
the offset register of the selected channel.
Internal Full-Scale Calibration.
The fullscale input is automatically connected to the selected analog input for this calibration. When the gain
equals 1, a calibration takes 2 conversion cycles to complete. For higher gains, 4 conversion cycles are
required for the fullscale calibration. RDY goes high when the calibration is initiated and returns low when
the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale
calibration coefficient is placed in the fullscale register of the selected channel. A fullscale calibration is
required each time the gain of a channel is changed. The full-scale error of the AD7799/AD7798 is calibrated
in the factory at both a gain of 1 and 128. These values are loaded into the fullscale register when the gain is 1
or 128. If a different PGA gain is used, then an Internal Full-Scale Calibration is required to calibrate out the
gain error associated with that PGA gain. Note that Internal Fullscale Calibrations cannot be performed at a
gain of 128.
System Offset Calibration.
User should connect the system zero-scale input to the channel input pins as selected by the CH2-CH0 bits.
A system offset calibration takes 2 conversion cycles to complete. RDY goes high when the calibration is
initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a
calibration. The measurded offset calibration coefficient is placed in the offset register of the selected
channel.
System Full-Scale Calibration.
User should connect the system full-scale input to the channel input pins s selected by the CH2-CH0 bits. A
system full-scale calibration takes 2 conversion cycles to complete. RDY goes high when the calibration is
initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a
calibration. The measured full-scale calibration coefficient is placed in the fullscale register of the selected
channel.
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
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